Gate Types

Keywords: and, nand, or , nor, xor, xnor, buf, not.

Some of the gates supplied by Verilog are given above, to use a gate it has to be given inputs and allocated space to put its output. A name can be given to the gate but this is optional. The and and or gates have one output and can have two or more inputs. For example an and gate,

        and <name><list of arguments>
        and myand(out, in1, in2, in3); // legal and gate with three inputs
        and (out, in1, in2);           // legal gate with no name.

The buf and not gates each have one input and one or more outputs. The conventional is the same, the outputs come first and the last argument in the list is the input.

        buf mybuf(out1, out2, out3, in);
        not (out, in);

EXERCISE
a) Draw out the truth tables for a two input xnor gate.
b) What value of a is displayed ?

        module testgate;
           reg    b, c;
           wire   a, d, e;

           and (d, b, c);
           or (e, d, c);
           nand(a, e, b);

           initial begin
              b=1; c=0;
              #10 $display("a = %b", a);
           end

        endmodule

Answers