The four looping constructs in Verilog are
while,
for,
repeat
and
forever.
All of these can only appear inside
initial
and
always
blocks.
The basic idea of each of the loops is :
while:
executes a statement or set of statements while a condition is true.
for:
executes a statement or a set of statements.
This loop can initialise, test and increment the index
variable in a neat fashion.
repeat:
executes a statement or a set of statements a fixed number of times.
forever:
executes a statement or a set of statements forever and ever, or until
the simulation is halted.