Connection Rules

We will talk of two type of modules, the outer and inner modules, as as analogy the outer module is the E-type and the inner module is the D-type. It might be useful to take a look at the section on modules to understand this.

1. Inputs

In an inner module inputs must always be of a net type, since values will be driven into them. In the outer module the input may be a net type or a reg.

2. Outputs

In an inner module outputs can be of a net type or a reg. In an outer module the output must be of a net type since values will be driven into them by the inner module.

3. Inouts

Inouts must always be of a net type.
EXERCISE: Why? is this the case, the answer follows from the above sections.

4. Port Matching

When calling a module the width of each port must be the same, eg, a 4-bit register cannot be matched to a 2-bit register.

However, output ports may remain unconnected, by missing out their name in the port list. This would be useful if some outputs were for debugging purposes or if some outputs of a more general module were not required in a particular context. However input ports cannot be omitted for obvious reasons.

For example:

        d_ff dff0(  , d, reset, clock); // the output (q) has been omitted
                                        // the comma is ESSENTIAL

Connecting Ports

Ports can be connected by either ordered list or by name. The ordered list method is recommended for the beginner, in this method the port list in the module instantiation is in the same order as in the module definition. See example below.

        module d_ff( q, d, reset, clock);
             ...
        endmodule

        module e_ff(q, d , enable, reset, clock);
             output q;
             input d, enable, reset, clock;
             wire inD;
                    ...
             d_ff dff0(q, inD, reset, clock);
                    ...
        endmodule

The second method is by name, when instantiating, the ports in the definition are accompanied by the corresponding port name in the instantiation. EXERCISE
a) Draw a diagram for your own reference illustrating the constraints on the input, output and inouts.
b) Using the module interfaces for the d_ff and the e_ff modules above, write code to complete them AND a toggle flip-flop: t_ff, based upon a call to the e_ff module. The function of the toggle flipflop is to either change its output or to hold its output on each new rising clock edge according to a control signal: toggle. It should also have a synchronous reset.

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