X, Z In IF Conditions

And CaseX, CaseZ

Logic Levels Within Verilog

An x can be any one of a 1, 0, z or change of state. If a one and a zero are both present at a node with comparable strength, the resultant is unknown (x).

A z represents a high impedance or floating gate condition. It is the weakest level of logic, being very susceptible to change, and primarily occurs when a node is no longer driven.

X, Z in IF and CASE statements

Within an IF statement a zero corresponds to a false condition and any other value to true. However, if an unknown (x) or high impedance (z) are compared the result may evaluate to an x or z, being interpreted as a false condition.

Case expressions may include x's and z's, with the comparison only being successful if there is an exact match between each individual bit (whether it be a 0, 1, x ot z).

X, Z In CASEX, CASEZ

Casex and casez are the two variations of the case statement within Verilog. The syntax is almost identical to the case statement, with the only difference being that case is substituted by either casex or casez. The syntax is as follows:

The use of casex and casez allows don't care values to be considered in the comparison. Casez allows for z values to be treated as don't cares, whereas casex allows for both z and x to be treated as don't cares. Only bit values other than the don't care bits are used in the comparison.

An example of the use of x within a casex statement is given below:

Where the ^ character represents the Exclusive-OR function.

Assuming value_read is given as 11001001 the statement executed is calculated as follows:

Note: when an x is Exclusive-ORed with any value the result is an x.

It can be seen that the only statement the match and therefore the one which is executed is statement3.