This section explains what a parameterized module is and the syntax involved initialising and re-defining parameter values.
A description of a parameter and the syntax involved in its declaration are explained here.
There are two methods used to re-define a parameter they are explained by the following:
A parameter is defined by Verilog as a constant value declared within the module structure. The value can be used to define a set of attributes for the module which can characterize its behaviour as well as its physical representation.
To declare a parameter within a module the keyword parameter is used as shown in the following example.
module MyModule( out, clock, inA, inB);
parameter BusWidth = 8, GateDelay = 5;
output out;
input clock, inA, inB;
wire [BusWidth - 1: 0] DataBus; // using the BusWidth parameter to define the number of wires in DataBus
.
.
always @(posedge clock)
if( inA == 1 )
#GateDelay out = ~ InA; // using the GateDelay parameter to define the gate propogation delay.
.
endmodule // end MyModule
A further beneficial property of using parameters is that there value can be changed externally. There are two methods which can be used to over-ride the default parameter values - using the defparam syntax or define the parameter values at module instantiation.
The following example shows the syntax required to alter a parameter value using defparam.
// Using defparam
module TopLevel ( out, clock, inX, inY);
output out;
input clock, inX, inY;
.
.
defparam Inst1.GateDelay = 2; // using defparam to change the GateDelay parameter
.
MyModule Inst1( out, clock, inX, inY); // module instantiation
.
endmodule //end TopLevel
This technique has the benefit that the parameter to be re-defined is explicitally declared from within the calling module. The `.' notation is used to access the particular parameter using a similar method to accessing a variable encapsulated within a 'C' language data structure (struct). This technique also allows for multiple calls to be made from within a module, allowing parameters to be changed at different time intervals if required. This differs it from the next technique which only allows parameters to be re-defined at the module instantiation.
The following example shows the syntax required to alter a parameter value at module instantiation.
// Using module instantiation
module TopLevel( out, clock, inX, inY);
output out;
input clock, inX, inY;
MyModule #( 8, 20 ) Inst1 ( out, clock, inX, inY); // over-riding parameters at module instantiation
.
endmodule // end TopLevel
Notice that using the module instantiation technique the parameters are re-defined using the # operator, followed by a list of values. The order of the listing is important because they map directly to the parameter declarations in that order. In the example above the #( 8, 20 ) re-defines the parameters; BusWidth = 8 and GateDelay = 20. Thus, in this case only the gate delay has actually been changed, the bus width remains at its default value. To change only the gate delay only using this technique would require that this parameter be declared first in the module MyModule, this could then be re-defined using the #( 20 ), to change only the gate delay. Therefore, every preceding parameter including the target parameters must be re-defined using this technique.