Verilog HDL : Signal Strengths

Introduction :

The ability to model varying signal levels as produced by digital hardware is fundamentally important for the simulation of switch level circuits. This is accomplished by assigning various signal strengths as defined in Table 1. The signal strengths vary from supply level own to high impedence level, covering six distinct intermediate levels. Each level can represent a logic 1 (supply1, strong 1 ..... highz1) or a logic 0 (supply0, strong0 ..... highz0).

Table 1 : Signal strength definitions.
Strength Name	Strength Level	Element Modelled	Declaration Abbreviation
Supply Drive	7	Power supply connections.	supply
Strong Drive	6	Default gate & assign output strength.	strong
Pull Drive	5	Gate & assign output strength.	pull
Large Capacitor	4	Size of trireg net capacitor.	large
Weak Capacitor	3	Gate & assign output strength.	weak
Medium Capacitor	2	Size of trireg net capacitor.	medium
Small Capacitor	1	Size of trireg net capacitor.	small
High Impedence	0	Not Applicable.	highz

Signal strengths are used by the Verilog simulator in two main situations : modelling of weak (resistive) transistors and resolving signal contention.

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Modelling of weak (resistive) transistors :

Weak or resistive transistors have many uses within the domain of digital design. A property associated with resistive transistors is that any signal passed through one is degraded. This is modelled within Verilog using signal strengths which are reduced when they encounter resistive transistors. Signals are degraded as indicated in Table 2.

Table 2: Signal degradation through a resistive transistor as modelled by Verilog
Input Strength	Output Strength
supply	pull
strong	pull
pull	weak
weak	medium
large	medium
medium	small
small	small
highz	highz

One such occasion where this technique is needed is for the digital latch (Figure 1), where a weak transistor is used to reinforce the poor logic 1 passed by the transmission gate. The logic 1 imposed by this weak transistor can however be overcome by the strong logic 0 passed by the transmission gate.

Figure 1 : simple latch circuit exhibiting signal contention.

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Resolving signal contention :

The situation often arises whereby two signals drive one node in a circuit resulting in signal contention (Figure 2). The strength and logic value of the two signals are used to resolve the signal conflict to produce a single logic value and strength on the node.

Three situations can arise.

The signals are logically the same but of different strength (Figure 2a) resulting in the output node having the same logic value and a strength equal to the strongest input signal.
The signals are of the same strength but logically opposite (Figure 2b) resulting in an unknown signal of the same strength.
The signals are logically opposite and of different strength (Figure 2c) resulting in an ambiguous signal

Figure 2 : a) Similar logic, strength contention.
b) Similar strength, logic contention.
c) Logic and strength contention.

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Any problems or queries email :

S.I.Penman@ug.ee.ed.ac.uk

Introduction :

Strength Name

Strength Level

Element Modelled

Declaration Abbreviation

Modelling of weak (resistive) transistors :

Input Strength

Output Strength