module full_adder(sum_out, carry_out, a, b, carry_in);
   
   /*
    * A gate-level model of a 1-bit full-adder
    */
   
   output carry_out, sum_out;
   input  carry_in, a, b;
   wire	  one_high, generate, propagate;
   
   xor x0(one_high, a, b);
   xor x1(sum_out, one_high, carry_in);
   and a0(generate, a, b);
   and a1(propagate, one_high, carry_in);
   or  o0(carry_out, generate, propagate);
   
endmodule /* full_adder */

module ripple_carry_4_bit(sum_out, carry_out, a, b, carry_in);

   /*
    *  A gate-level model of a 4-bit ripple carry adder
    */

   output [3:0]	sum_out;
   output	carry_out;
   input [3:0]	a, b;
   input	carry_in;
   wire [2:0]	ripple;
		
   full_adder f_a0(sum_out[0], ripple[0], a[0], b[0], carry_in);
   full_adder f_a1(sum_out[1], ripple[1], a[1], b[1], ripple[0]);
   full_adder f_a2(sum_out[2], ripple[2], a[2], b[2], ripple[1]);
   full_adder f_a3(sum_out[3], carry_out, a[3], b[3], ripple[2]);

endmodule /* ripple_carry_4_bit */
	   

module stimulus; 

   reg [3:0]  a, b;
   reg	      c_in;
   wire [3:0] s_out;
   wire	      c_out; 
   reg	      clk;  
   
   integer    i;
   ripple_carry_4_bit r_c0(s_out, c_out, a, b, c_in);
   
   initial 
      $gr_waves("c_in", c_in, "b[0]", b[0], "b[1]", b[1], "b[2]", b[2], "b[3]", b[3],
		"a[0]", a[0], "a[1]", a[1], "a[2]", a[2], "a[3]", a[3], 
		"sum[0]", s_out[0], "sum[1]", s_out[1], "sum[2]", s_out[2],
		"sum[3]", s_out[3], "c_out", c_out, "clk", clk);
 
   initial begin
      clk = 1'b0;
      forever clk = #1 ~clk;
   end	   
   
   initial begin
      $display("a\tb\tcarry_in\tcarry_out\tsum_out\n");
      for(i = 0; i < 512; i = i + 1) begin
	 {a, b, c_in} = i[8:0];
	 #50 $display("%b\t%b\t   %b\t\t    %b\t\t   %b", 
		      a, b, c_in, c_out, s_out);
      end
      #50 $stop;   
   end
	   
endmodule /* stimulus */