module full_adder(sum_out, carry_out, a, b, carry_in);
   
   /*
    * A gate-level model of a 1-bit full-adder
    */
   
   output carry_out, sum_out;
   input  carry_in, a, b;
   wire	  one_high, generate, propagate;
   
   xor x0(one_high, a, b);
   xor x1(sum_out, one_high, carry_in);
   and a0(generate, a, b);
   and a1(propagate, one_high, carry_in);
   or  o0(carry_out, generate, propagate);
   
endmodule /* full_adder */

module stimulus;
   
   reg	a, b, c_in;
   wire	s_out, c_out;
   reg	clk;
   
   integer i;
   full_adder f_a0(s_out, c_out, a, b, c_in);

   initial
      $gr_waves("c_in", c_in, "b", b, "a", a, "sum", s_out, "c_out", c_out, 
		"clk", clk);

   initial begin
      clk = 1'b0;
      forever clk = #1 ~clk;
   end	   
   
   initial begin
      $display("a\tb\tcarry_in\tcarry_out\tsum_out\n");
      for(i = 0; i <= 8; i = i + 1) begin
	 {a, b, c_in} = i[2:0];
	 #10 $display("%b\t%b\t   %b\t\t    %b\t\t   %b", 
		      a, b, c_in, c_out, s_out);
      end
      #10 $stop;
   end
   
endmodule /* stimulus */