WISHBONE SoC Patent References

The patents listed below have been reviewed by Silicore Corporation to determine if the WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores infringes on the rights of others. It is also used to determine if any newly issued patent attempts to protect technologies that have already been placed into the public domain by the WISHBONE specification. This is not a comprehensive list and should not be used as a substitute for legal counsel. The user assumes all responsibility for determining if their WISHBONE SoC component infringes on the intellectual property rights of others. Submissions to this list are encouraged, and should be sent to: wadep@silicore.net.

Patent documents and searchable databases are available on-line from:

 

Motivation(s) for the Patent Review

There are several reasons for reviewing these patents. The most important is to prevent patented technologies from entering the public WISHBONE architecture. That's because WISHBONE is an enabling technology for an open System-on-Chip marketplace. By definition, an open technology market can't be based around proprietary technologies. If it were, then the owner of the intellectual property could unfairly manipulate the market to their own advantage. Defending the public domain status of the WISHBONE interconnection creates a technological safe harbors for those participating in the market.

It should be noted that the public domain status of WISHBONE only refers to the commons area of the System-on-Chip. No attempt is made to protect anything beyond the WISHBONE interface (e.g. IP Cores) or the standard interconnections listed in the specification (e.g. the standard shared bus). This means that users are free to protect their IP cores and novel interconnections using the patent, copyright and trademark system if they wish.

In theory, it shouldn't even be necessary to review these patents. That's because most patent offices won't issue a patent unless it is for a novel invention, meaning that it hasn't been thought of before. However, inventors and patent examiners may not necessarily be aware of WISHBONE technology because it's been placed into the public domain by publishing it on the internet (i.e. it's a public works of invention). This means that it doesn't appear in the patent file system. It also means that the only way to defend the WISHBONE commons area is by monitoring new patents.

The US Patent system does provide something called a statutory invention registration under 35 U.S.C. 157. These don't have the traditional, enforceable attributes of a patent, but can be defended to prevent others from protecting the same invention. In theory, the invention registration could be used to defend the WISHBONE commons area. However, in this case it isn't practical because: (a) they are too expensive to obtain and (b) technology innovations come from many users around the globe...usually in the form of published cores and interconnections. Instead, the WISHBONE commons area is defended by monitoring new patents in a timely manner, and if trouble arises forming a posse of interested parties to defend it. This same approach has worked very well in the past on the VMEbus commons, and there is good evidence that the same strategy works in the GNU/Linux world as well.

The list of patent references also provides a good starting point for IC system designers and other researchers who need to know if a specific SoC design infringes on the rights of others. For example, a crossbar switch designer can read other patents on the same subject. The patent documents are also a good place to learn how other people have solved similar problems. They are very good in this regard, as they must fully describe how to reproduce an invention.

An excellent resource about intellectual property and the public domain can be found at the Duke University Law School - Center for the Study of the Public Domain (http://www.law.duke.edu/cspd/).

 

Backlog Delay at the PTO

The US Patent and Trademark Office (PTO) has a backlog delay due to the high volume of applications that it handles. The backlog delay is the time interval between a patent's application date and its issue date.

The backlog delay is important for public domain engineering projects like WISHBONE because it can take several years before a patented invention can be found. For example, if a new feature is added to the WISHBONE specification, then it can take some time to figure out if somebody else had already invented it. Currently [2003], the average backlog delay for the WISHBONE SoC Patent References is 29.5 months. To view a graph of the backlog delay, click here.

 

Search Criteria

All of these documents contain information relevant to SoC design and integration. Patents recently added to the list are marked '[*NEW*]', irrespective of the patent issue date. Currently the list only shows US patents. Other examples in this field of invention can be found at: www.silicore.net\uCbusum.htm

The following key words and phrases are helpful for patent searches: "crossbar switch"; "data flow"; "gate array"; "IP"; "IP Core"; "Network-on-Chip"; "network on chip"; "NoC"; "PLD"; "RTL"; "SoC"; "System-on-Chip"; "system on chip"; "tagged architecture" and "WISHBONE".

 

SoC: General Methods

Hartmann, Alfred C. - US Patent No. 6,096,091
DYNAMICALLY RECONFIGURABLE LOGIC NETWORKS INTERCONNECTED BY FALL-THROUGH FIFOS FOR FLEXIBLE PIPELINE PROCESSING IN A SYSTEM-ON-A-CHIP

Hofmann et al. - US Patent No. 6,513,089
DUAL BURST LATENCY TIMERS FOR OVERLAPPED READ AND WRITE DATA TRANSFERS

Luk et al. - US Patent No. 5,790,839
SYSTEM INTEGRATION OF DRAM MACROS AND LOGIC CORES IN A SINGLE CHIP ARCHITECTURE

Luk et al. - US Patent No. 5,883,814
SYSTEM-ON-CHIP LAYOUT COMPILATION

Malladi - US Patent No. 5,870,310
METHOD AND APPARATUS FOR DESIGNING RE-USABLE CORE INTERFACE SHELLS

San Juan - US Patent No. 6,418,491 (B1)
APPARATUS AND METHOD FOR CONTROLLING TIMING OF TRANSFER REQUESTS WITHIN A DATA PROCESSING APPARATUS.

Stevens - US Patent No. 6,064,626
PERIPHERAL BUSES FOR INTEGRATED CIRCUIT

Weber et al. - US Patent No. 6,330,225 (B1)
COMMUNICATION SYSTEM AND METHOD FOR DIFFERENT QUALITY OF SERVICE GUARANTEES FOR DIFFERENT DATA FLOWS

Wingard et al. - US Patent No. 5,948,089
FULLY-PIPELINED FIXED-LATENCY COMMUNICATIONS SYSTEM WITH A REAL TYPE DYNAMIC BANDWIDTH ALLOCATION.

Wingard et al. - US Patent No. 6,182,183 (B1)
COMMUNICATION SYSTEM AND METHOD WITH MULTILEVEL CONNECTION IDENTIFICATION

Zaidi et al. - US Patent No. 6,601,126 (B1) [*NEW*]
CHIP CORE FRAMEWORK FOR SYSTEMS-ON-A-CHIP
Read an opinion about this patent at: www.silicore.net/US06601126.htm

 

SoC: Design Automation

Some patents relating to other forms of SoC design automation are shown elsewhere on this page. The section entitled "SoC: Embedded Logic Analyzer" includes some SoC logic analyzers that are generated with design automation tools. The section entitled "SoC: 'C' Language Implementations" describe design automation tools for writing SoC applications with the 'C' programming language.

Bergamashi/Rab et al.- US Patent No. 6,477,691 (B1)
METHODS AND ARRANGEMENTS FOR AUTOMATIC SYNTESIS OF SYSTEMS-ON-CHIP

Chang et al.- US Patent No. 6,269,467 (B1)
BLOCK BASED DESIGN METHODOLOGY

Chang et al.- US Patent No. 6,567,957 (B1)
BLOCK BASED DESIGN METHODOLOGY

Devins et al.- US Patent No. 6,427,224 (B1)
METHOD FOR EFFICIENT VERIFICATION OF SYSTEM-ON-CHIP INTEGRATED CIRCUIT DESIGNS INCLUDING AN EMBEDDED PROCESSOR

Devins et al.- US Patent No. 6,487,699 (B1)
METHOD OF CONTROLLING EXTERNAL MODELS IN SYSTEM-ON-CHIP VERIFICATION

Devins et al.- US Patent No. 6,539,522 (B1)
METHOD OF DEVELOPING RE-USABLE SOFTWARE FOR EFFICIENT VERIFICATION OF SYSTEM-ON-CHIP INTEGRATED CIRCUIT DESIGNS

Gardner et al.- US Patent No. 6,446,251 (B1)
METHOD AND APPARATUS FOR SOCKET-BASED DESIGN WITH REUSABLE-IP

Huang et al. - US Patent No. 6,446,243 (B1)
METHOD FOR FUNCTIONAL VERIFICATION OF VLSI CIRCUIT DESIGNS UTILIZING REUSABLE FUNCTIONAL BLOCKS OR INTELLECTUAL PROPERTY CORES

Lee et al. - US Patent No. 5,563,801
PROCESS INDEPENDENT DESIGN FOR GATE ARRAY DEVICES

Lee et al. - US Patent No. 6,102,961
METHOD AND APPARATUS FOR SELECTING IP BLOCKS

Squires - US Patent No. 6,510548 (B1)
METHOD FOR PROVIDING PRE-DESIGNED MODULES FOR PROGRAMMABLE LOGIC DEVICES

 

SoC: Embedded Logic Analyzers

Edwards et al.- US Patent No. 6,298,394 (B1)
SYSTEM AND METHOD FOR CAPTURING INFORMATION ON AN INTERCONNECT IN AN INTEGRATED CIRCUIT

Herrmann et al.- US Patent No. 6,389,558 (B1)
EMBEDDED LOGIC ANALYZER FOR A PROGRAMMABLE LOGIC DEVICE

Flynn, David W. - US Patent No. 5,525,971
INTEGRATED CIRCUIT

Veenstra et al.- US Patent No. 6,460,148 (B2)
ENHANCED EMBEDDED LOGIC ANALYZER

 

SoC: 'C' Language System Implementations

Sato et al. - US Patent No. 6,467,075 (B1)
RESOLUTION OF DYNAMIC MEMORY ALLOCATION/DEALLOCATION AND POINTERS

Venkitakrishnan - US Patent No. 6,513,145 (B1)
METHOD FOR ESTIMATING THE POWER CONSUMED IN A MICROPROCESSOR

 

SoC: Variable Clock Frequency

Gandhi et al. - US Patent No. 6,185,691 (B1)
CLOCK GENERATION

Kardach et al. - US Patent No. 5,473,767
METHOD AND APPARATUS FOR ASYNCHRONOUSLY STOPPING THE CLOCK ON A PROCESSOR.

Kardach et al. - US Patent No. 5,918,043
METHOD AND APPARATUS FOR ASYNCHRONOUSLY STOPPING THE CLOCK ON A PROCESSOR.

Maitra, Amit K. - US Patent No. 5,623,647
APPLICATION SPECIFIC CLOCK THROTTLING

Orton et al. - US Patent No. 6,118,306
CHANGING CLOCK FREQUENCY

Poplingher et al. - US Patent No. 6,173,379 (B1)
MEMORY DEVICE FOR A MICROPROCESSOR REGISTER FILE HAVING A POWER MANAGEMENT SCHEME AND METHOD FOR COPYING INFORMATION BETWEEN MEMORY SUB-CELLS IN A SINGLE CLOCK CYCLE

Stinson et al. - US Patent No. 6,127,858
METHOD AND APPARATUS FOR VARYING A CLOCK FREQUENCY ON A PHASE BY PHASE BASIS

Thomas, Thomas P. - US Patent No. 6,140,883
TUNABLE, ENERGY EFFICIENT CLOCKING SCHEME

Wong et al. - US Patent No. 5,586,307
METHOD AND APPARATUS SUPPLYING SYNCHRONOUS CLOCK SIGNALS TO CIRCUIT COMPONENTS

Young, Bruce - US Patent No. 6,079,022
METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING THE CLOCK SPEED OF A BUS DEPENDING ON BUS ACTIVITY

 

IP Cores: Security

McManus et al. - US Patent No. 6,525,557 (B1)
METHOD FOR WATERMARKING A REGISTER-BASED PROGRAMMABLE LOGIC DEVICE CORE

 

IP Cores: Testability

Stevens.- US Patent No. 6,463,488 (B1)
APPARATUS AND METHOD FOR TESTING MASTER LOGIC UNITS WITHIN A DATA PROCESSING APPARATUS

Whetsel.- US Patent No. 6,223,315 (B1)
IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION

 

Interconnection: Data Flow

Cismas, Sorin C. - US Patent No. 6,145,073
DATA FLOW INTEGRATED CIRCUIT ARCHITECTURE

 

Interconnection: Crossbar Switch

Brewer et al. - US Patent No. 5,577,204
PARALLEL PROCESSING COMPUTER SYSTEM INTERCONNECTIONS UTILIZING UNIDIRECTIONAL COMMUNICATION LINKS WITH SEPARATE REQUEST AND RESPONSE LINES FOR DIRECT COMMUNICATION OR USING A CROSSBAR SWITCHING DEVICE

Nelson et al. - US Patent No. 6,138,185
HIGH PERFORMANCE CROSSBAR SWITCH

Spaderna et al. - US Patent No. 6,331,977 (B1)
SYSTEM ON CHIP (SOC) FOUR-WAY SWITCH CROSSBAR SYSTEM AND METHOD

Van Krevelen et al. - US Patent No. 6,230,229 (B1)
METHOD AND SYSTEM FOR ARBITRATING PATH CONTENTION IN A CROSSBAR INTERCONNECT NETWORK

 

Interconnection: Interrupts

Stevens. - US Patent No. 6,424,179 (B1)
LOGIC UNIT AND INTEGRATED CIRCUIT FOR CLEARING INTERRUPTS

 

Interconnection: Tagged Architectures

An excellent overview of the early history of tagged architectures can be found in: Feustel, Edward A. "On The Advantages of Tagged Architecture" IEEE Transactions on Computers, Vol C-22, No. 7, July 1973. The article describes early prior art on tagged architectures that are similar to WISHBONE. According to Feustel, the first tagged architecture was used on the Brookhaven National Laboratories MERLIN machine in 1957.

Cahill et al. - US Patent No. 6,021,272
TRANSFORMING AND MANIPULATING PROGRAM OBJECT CODE

Dulong et al. - US Patent No. 6,163,764
EMULATION OF AN INSTRUCTION SET ON AN INSTRUCTION SET ARCHITECTURE TRANSITION

Eustace et al. - US Patent No. 5,613,063
METHOD AND APPARATUS FOR CHECKING VALIDITY OF MEMORY OPERATIONS

Hastings - US Patent No. 5,535,329
METHOD AND APPARATUS FOR MODIFYING RELOCATABLE OBJECT CODE FILES AND MONITORING PROGRAMS

Hastings - US Patent No. 5,835,701
METHOD AND APPARATUS FOR MODIFYING RELOCATABLE OBJECT CODE FILES AND MONITORING PROGRAMS

Hastings - US Patent No. 6,206,584
METHOD AND APPARATUS FOR MODIFYING RELOCATABLE OBJECT CODE FILES AND MONITORING PROGRAMS

O'Connor et al. - US Patent No. 5,845,298
WRITE BARRIER SYSTEM AND METHOD FOR TRAPPING GARBAGE COLLECTION PAGE BOUNDARY CROSSING POINTER STORES

O'Connor et al. - US Patent No. 5,953,736
WRITE BARRIER SYSTEM AND METHOD INCLUDING POINTER-SPECIFIC INSTRUCTION VARIANT REPLACEMENT MECHANISM

O'Connor et al. - US Patent No. 6,098,089
GENERATION ISOLATION SYSTEM AND METHOD FOR GARBAGE COLLECTION

Pentovski et al. - US Patent No. 6,185,671
CHECKING DATA TYPE OF OPERANDS SPECIFIED BY AN INSTRUCTION USING ATTRIBUTES IN A TAGGED ARRAY ARCHITECTURE

Shinozaki et al. - US Patent No. 5,493,662
APPARATUS FOR ENABLING EXCHANGE OF DATA OF DIFFERENT LENGTHS BETWEEN MEMORIES OF AT LEAST TWO COMPUTER SYSTEMS

This page last updated: 9 Nov 2003

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