IDE Disk Interface Suggestion from Diego Trampus:
A 95xx would be used with all 16 address lines used to decode say an IO map
of 16 bytes, 10 (ie: 0-9) would be used by the IDE (as below), while A-F
could be used for ANY other purpose, eg: A/B for a mc14681, C/F for a
6821/6551/etc.
IDE Registers
====================================================
cs[1:0] a[2:0] Read Write Size 6x09* (*see below
----------------------------------------------------
1 6 AltStatus DevControl Byte 0
2 0 Data16 Data16 Word 8&9
2 1 Error Features Byte 1
2 2 SecCount SecCount Byte 2
2 3 SecNum SecNum Byte 3
2 4 CylLo CylLo Byte 4
2 5 CylHi CylHi Byte 5
2 6 DevHead DevHead Byte 6
2 7 Status Command Byte 7
----------------------------------------------------
NB: All other options do NOT access the IDE ! (ie:cs=3)
----------------------------------------------------
6x09 Access to IDE registers (0 to 9)
=========================================================================
Access to Data16 is normally via LDD/STD instructions.
Writing the MSB (8) latches it, while writing the LSB (9) writes a WORD to
the IDE.
Reading the MSB (8) reads a WORD from the IDE, latches the LSB and puts the
MSB on the CPU data bus. Reading the LSB (9), just reads the latched data.
All other addresses are BYTE size. Access to 6x09 registers (0 to 7) cause
the 95xx to output the appropriate signals for cs[1:0], a[2:0], etc.
ie: 6x09 register 0 is maps to IDE register cs[1:0]=1, a[2:0]=6
6x09 register 1 is maps to IDE register cs[1:0]=2, a[2:0]=1
6x09 register 2 is maps to IDE register cs[1:0]=2, a[2:0]=2
6x09 register 3 is maps to IDE register cs[1:0]=2, a[2:0]=3
6x09 register 4 is maps to IDE register cs[1:0]=2, a[2:0]=4
6x09 register 5 is maps to IDE register cs[1:0]=2, a[2:0]=5
6x09 register 6 is maps to IDE register cs[1:0]=2, a[2:0]=6
6x09 register 7 is maps to IDE register cs[1:0]=2, a[2:0]=7
----------------------------------------------------------------
Rd 6x09 register 8 is maps to IDE register cs[1:0]=2, a[2:0]=0, & latches LSB
Rd 6x09 register 9 read the prior latched LSB.
----------------------------------------------------------------
Wr 6x09 register 8 latches MSB
Wr 6x09 register 9 is maps to IDE register cs[1:0]=2, a[2:0]=0, outputs MSB.
----------------------------------------------------------------
6x09 register A-F cause cs[2:0] to 3 (ie: disable IDE), but COULD be used
to enable other devices. eg: A-B could enable ANOTHER device such as
a RTC, and C-F are also available for say a PIA/ACIA/etc.
===================================================
When the IDE cs[1:0]=3, then the IDE is DISABLED,
some of the IDE signals can be used for other duties.
---------------------------------------------------
IDE Examples for Alternate Use.
d0-d7 No change (Low Order Data Bus)
d8-d15 Buffered Address Bits a8-a15
a0-a2 Buffered Address Bits a16-a18
----------------------------------------------------
Other IDE signals used/needed are:-
INT O Active HI Interrupt Request (Needs to be INVERTED for 6x09)
/RST I Active LO Reset (could also do s/w RESET)
/ACT O Active LO Device Active (Just a LED display)
I've got a document, about 280k, (xt310/200d-rev6)
Information Technology-AT Attachment-3 Interface (ATA-3),
that fully descibes ALL signals on an IDE interface.
============================================================
From Tommy's Pinouts
http://csgrad.cs.vt.edu/~tjohnson/pinouts/
IDE drive connector
Connector: 40 pin header IDE Hard Disk Interface IDC-40 Male pin assignment pin assignment 1 -Reset 2 GND 3 Data 7 4 Data 8 5 Data 6 6 Data 9 7 Data 5 8 Data 10 9 Data 4 10 Data 11 11 Data 3 12 Data 12 13 Data 2 14 Data 13 15 Data 1 16 Data 14 17 Data 0 18 Data 15 19 GND 20 Key 21 (reserved) 22 GND 23 -IOW 24 GND 25 -IOR 26 GND 27 IO Chrdy 28 Ale 29 (reserved) 30 GND 31 IRQ14 32 -IOCS16 33 Addr 1 34 (reserved) 35 Addr 0 36 Addr 2 37 -CS0 (1F0-1F7) 38 -CS1 (3f6-3f7) 39 -Active 40 GND