Displaying Complex Strings in Assert Statements

A common use of assert and report statements is to display information about signals or variables dynamically during a simulation run. Unfortunately, VHDL’s built-in support for this is somewhat limited. The problem is twofold: first, the report clause only accepts a single string as its argument, so it is necessary to either write multiple assert statements to output multiple lines of information (as when formatting and displaying a table), or you must make use of the string concatenation operator & and the special character constant CR (carriage return) and/or LF (line feed) to describe a single, multi-line string as shown below:

assert false

report "This is the first line of the message." & CR & LF &

"This is the second line of the message.";

The second, more serious limitation of the report statement clause is that it only accepts a string, and there is no built-in provision for formatting various types of data (such as arrays, integers and the like) for display. This means that to display such data in an assert statement, you must provide type conversion functions that will convert from the data types you are using to a formatted string. The following example (which is described in more detail later in this chapter) demonstrates how you might write a conversion function to display a std_logic_vector array value as a string of characters:

architecture stimulus of testfib is

. . .

function vec2str(vec: std_logic_vector) return string is

variable stmp: string(vec’left+1 downto 1);

begin

for i in vec’reverse_range loop

if (vec(i) = ‘U’) then

stmp(i+1) := ‘U’;

elsif (vec(i) = ‘X’) then

stmp(i+1) := ‘X’;

elsif (vec(i) = ‘0’) then

stmp(i+1) := ‘0’;

elsif (vec(i) = ‘1’) then

stmp(i+1) := ‘1’;

elsif (vec(i) = ‘Z’) then

stmp(i+1) := ‘Z’;

elsif (vec(i) = ‘W’) then

stmp(i+1) := ‘W’;

elsif (vec(i) = ‘L’) then

stmp(i+1) := ‘L’;

elsif (vec(i) = ‘H’) then

stmp(i+1) := ‘H’;

else

stmp(i+1) := ‘-’;

end if;

end loop;

return stmp;

end;

. . .

signal S: std_logic_vector(15 downto 0);

signal S_expected: std_logic_vector(15 downto 0);

begin

. . .

process

begin

. . .

assert (S /= S_expected) -- report an error if different

report "Vector failure!" & CR & LF &

"Expected S to be " & vec2str(S_expected) & CR & LF &

"but its value was " & vec2str(S)

severity ERROR;

In this example, a type conversion function has been written (vec2str) that converts an object of type std_logic_vector to a string of the appropriate format and size for display. As you develop more advanced test benches, you will probably find it useful to collect such type conversion functions into a library for use in future test benches.

As we will see in later sections of this document, there are other, more powerful ways to display formatted output, using the built-in text I/O features of the language.