mti_GetPrimaryName()

Gets the primary name of a region (entity, package, or module).

Syntax

primary_name = mti_GetPrimaryName( region_id ); 

Returns

Name	Type	Description
primary_name	char *	The primary name of the specified region

Arguments

Name	Type	Description
region_id	mtiRegionIdT	A handle to a VHDL or Verilog region

Description

mti_GetPrimaryName() returns the primary name of the specified VHDL or Verilog region (that is, an entity, package, or module name). If the region is not a primary design unit, then the parent primary design unit is used.

The returned pointer must not be freed.

Related functions

mti_GetLibraryName()

mti_GetRegionFullName()

mti_GetRegionName()

mti_GetRegionSourceName()

mti_GetSecondaryName()

Example

FLI code

#include <mti.h>

static void printRegionInfo( char * region )
{
  char *       primary_name;
  char *       region_name;
  mtiRegionIdT regid;

  regid        = mti_FindRegion( region );
  region_name  = mti_GetRegionFullName( regid );
  primary_name = mti_GetPrimaryName( regid );
  mti_PrintFormatted( "  Region %s; Primary name is %s\n",
                     region_name, primary_name );
  mti_VsimFree( region_name );
}

static void initInstance( void )
{
  mti_PrintFormatted( "Load Done Callback Function:\n" );
  printRegionInfo( "/top" );
  printRegionInfo( "/top/linst1" );
  printRegionInfo( "/top/linst2" );
  printRegionInfo( "/top/finst" );
  printRegionInfo( "/for_pkg" );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  char * primary_name;
  char * region_name;

  mti_PrintFormatted( "Foreign Init Function:\n" );
  region_name = mti_GetRegionFullName( region );
  primary_name = mti_GetPrimaryName( region );
  mti_PrintFormatted( "  Region parameter is %s; Primary name is %s\n",
                     region_name, primary_name );
  mti_VsimFree( region_name );
  mti_AddLoadDoneCB( initInstance, 0 );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl;";
begin
end a;

package for_pkg is
  procedure test_proc;
end for_pkg;

package body for_pkg is
  procedure test_proc is
   begin
    assert false report "I'm in the test_proc." severity note;
   end;
end for_pkg;

use work.for_pkg.all;

entity lower is
end lower;

architecture level of lower is
begin
  p1 : process
   begin
    test_proc;
    wait for 20 ns;
   end process;
end level;

library ieee;
use ieee.std_logic_1164.all;

entity top is
end top;

architecture a of top is
  component for_model
  end component;

  component lower
  end component;

begin
  linst1 : lower;
  linst2 : lower;
  finst  : for_model;
end a;

configuration cfg_top of top is
  for a
   for all : lower
    use entity work.lower(level);
   end for;
   for all : for_model
    use entity work.for_model(a);
   end for;
  end for;
end cfg_top; 

Simulation output

% vsim -c cfg_top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c cfg_top 
# Loading .../modeltech/sunos5/../std.standard
# Loading .../modeltech/sunos5/../ieee.std_logic_1164(body)
# Loading work.for_pkg(body)
# Loading work.cfg_top
# Loading work.top(a)
# Loading work.lower(level)
# Loading work.for_model(a)
# Loading ./for_model.sl
# Foreign Init Function:
#   Region parameter is /top/finst; Primary name is for_model
# Load Done Callback Function:
#   Region /top; Primary name is top
#   Region /top/linst1; Primary name is lower
#   Region /top/linst2; Primary name is lower
#   Region /top/finst; Primary name is for_model
#   Region /for_pkg; Primary name is for_pkg
VSIM 1> run 20
# ** Note: I'm in the test_proc.
#    Time: 0 ns  Iteration: 0  Instance: /top/linst2
# ** Note: I'm in the test_proc.
#    Time: 0 ns  Iteration: 0  Instance: /top/linst1
# ** Note: I'm in the test_proc.
#    Time: 20 ns  Iteration: 0  Instance: /top/linst2
# ** Note: I'm in the test_proc.
#    Time: 20 ns  Iteration: 0  Instance: /top/linst1
VSIM 2> quit 

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