Detecting infinite zero-delay loops

Simulations use steps that advance simulated time, and steps that do not advance simulated time. Steps that do not advance simulated time are called "delta cycles". Delta cycles are used when signal assignments are made with zero time delay.

If a large number of delta cycles occur without advancing time, it is usually a symptom of an infinite zero-delay loop in the design. In order to detect the presence of these loops, ModelSim defines a limit, the "iteration_limit", on the number of successive delta cycles that can occur. When the iteration_limit is exceeded, vsim stops the simulation and gives a warning message.

The iteration_limit default value is 5000.When you get an iteration_limit warning, first increase the iteration limit and try to continue simulation. You can set the iteration_limit from the Options > Simulation menu, by modifying the modelsim.ini file, or by setting a Tcl variable called IterationLimit. See "Projects and system initialization" for more information on modifying the modelsim.ini file. And see "Preference variables located in Tcl files" for more information on Tcl variables.

If the problem persists, look for zero-delay loops. Run the simulation and look at the source code when the error occurs. Use the step button to step through the code and see which signals or variables are continuously oscillating. Two common causes are a loop that has no exit, or a series of gates with zero delay where the outputs are connected back to the inputs.

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