Verilog settings tab

The Verilog tab includes these options:

• Delay Selection (+mindelays | +typdelays | +maxdelays)
  Use the drop-down menu to select timing for min:typ:max expressions.

Pulse Options

• Disable pulse error and warning messages (+no_pulse_msg)
  Disables path pulse error warning messages.
• Rejection Limit (+pulse_r/<percent>)
  Sets the module path pulse rejection limit as a percentage of the path delay.
• Error Limit (+pulse_e/<percent>)
  Sets the module path pulse error limit as a percentage of the path delay.

Other Options

• Enable Hazard Checking (-hazards)
  Enables hazard checking in Verilog modules.
• Disable Timing Checks in Specify Blocks (+notimingchecks)
  Disables the timing check system tasks ($setup, $hold,...) in specify blocks.
• User Defined Arguments (+<plusarg>)
  Arguments are preceded with "+", making them accessible through the Verilog PLI routine mc_scan_plusargs. The values specified in this field must have a "+" preceding them or ModelSim may incorrectly parse them.

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