Component declaration

A Verilog module that is compiled into a library can be referenced from a VHDL design as though the module is a VHDL entity. The interface to the module can be extracted from the library in the form of a component declaration by running vgencomp. Given a library and module name, vgencomp writes a component declaration to standard output.

The default component port types are:

• std_logic
• std_logic_vector

Optionally, you can choose:

• bit and bit_vector
• vl_logic and vl_logic_vector

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