init_signal_spy()

The init_signal_spy() utility mirrors the value of a VHDL signal or Verilog register/wire (called the spy_object) onto an existing VHDL signal or Verilog register (called the dest_object). This allows you to reference signals, registers, or wires at any level of hierarchy from within a VHDL architecture (e.g., a testbench).

This system task works only in ModelSim versions 5.5 and newer.

Syntax

init_signal_spy( spy_object, dest_object, verbose); 

Returns

Nothing

Arguments

Name	Type	Description
spy_object	string	Required. A full hierarchical path (or relative path with reference to the calling block) to a VHDL signal or Verilog register/wire. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes.
dest_object	string	Required. A full hierarchical path (or relative path with reference to the calling block) to an existing VHDL signal or Verilog register. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes.
verbose	integer	Optional. Possible values are 0 or 1. Specifies whether you want a message reported in the Transcript stating that the spy_object's value is mirrored onto the dest_object. Default is 0, no message.

Related functions

None

Limitations

• When mirroring the value of a Verilog register/wire onto a VHDL signal, the VHDL signal must be of type bit, bit_vector, std_logic, or std_logic_vector.
• Mirroring slices or single bits of a vector is not supported. If you do reference a slice or bit of a vector, the function will assume that you are referencing the entire vector.

Example

library modelsim_lib;
use modelsim_lib.util.all;
entity top is
end;

architecture ...
  signal top_sig1 : std_logic;
begin
  ...
  spy_process : process
  begin
    init_signal_spy("/top/uut/inst1/sig1","/top_sig1",1);
    wait;
  end process spy_process;
  ...
end; 

In this example, the value of "/top/uut/inst1/sig1" will be mirrored onto
"/top_sig1".

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