Code Converters pins:
|
Pin Name |
Type |
Polarity Capable |
Description |
|
I1 -
In
|
in
|
No |
input data range
|
|
I
|
in
|
No |
input
|
|
EN
|
in
|
Yes |
EN='1' - converter enabled,
EN=
'0'converter
disabled<
/P><
/P><
/P><
/P>< /P>< /P><
/P>< /P> |
|
ER
|
out
|
Yes |
output error report
|
|
O
|
out
|
No |
output
|
|
O1-O7
|
out
|
No |
output range for
|
|
CE
|
in
|
Yes |
enables clock (for BCD to BIN, BIN to
BCD only)
|
|
CLK
|
in
|
Yes |
clock (for BCD to BIN, BIN to BCD
only)
|
|
CLR
|
in
|
Yes |
clears converter (for BCD to BIN, BIN
to BCD only)
|
The IP CORE Generator contains 16 code converters. The most
common codes are: binary, Gray and Johnson codes.
Binary code has the bit position weighted
as 8-4-2-1, respectively.
Gray code is exactly one bit
different between adjacent codes. The first eight codes are mirrored to
the last eight codes with the leftmost bit reserved. This property exists
recursively. For example, the first set of four codes (of the first eight
codes) is mirrored to the second set of four codes with the second
leftmost bit reversed.
|
Value
|
Codes
|
|
HOT, "one-1"
|
Binary 8-4-2-1
|
Gray
|
Johnson
|
7-seg
|
|
0
|
0000000001
|
0 0 0
0
|
0 0 0
0
|
0 0 0
0 0
|
0 1 1
1 1 1 1
|
|
1
|
0000000010
|
0 0 0
1
|
0 0 0
1
|
0 0 0
0 1
|
0 0 0
0 1 1 0
|
|
2
|
0000000100
|
0 0 1
0
|
0 0 1
1
|
0 0 0
1 1
|
1 0 1
1 0 1 1
|
|
3
|
0000001000
|
0 0 1
1
|
0 0 1
0
|
0 0 1
1 1
|
1 0 0
1 1 1 1
|
|
4
|
0000010000
|
0 1 0
0
|
0 1 1
0
|
0 1 1
1 1
|
1 1 0
0 1 1 0
|
|
5
|
0000100000
|
0 1 0
1
|
0 1 1
1
|
1 1 1
1 1
|
1 1 0
1 1 0 1
|
|
6
|
0001000000
|
0 1 1
0
|
0 1 0
1
|
1 1 1
1 0
|
1 1 1
1 1 0 0
|
|
7
|
0010000000
|
0 1 1
1
|
0 1 0
0
|
1 1 1
0 0
|
0 0 0
0 1 1 1
|
|
8
|
0100000000
|
1 0 0
0
|
1 1 0
0
|
1 1 0
0 0
|
1 1 1
1 1 1 1
|
|
9
|
1000000000
|
1 0 0
1
|
1 1 0
1
|
1 0 0
0 0
|
1 1 0
0 1 1 1
|
Available Options
You can select one of 16 available code converters: HOT to BIN, HOT
to Gray, HOT to Johnson, BCD to BIN, BCD to 7-seg, BIN to BCD, BIN to
7-seg, BIN to Gray, BIN to HOT, BIN to Johnson, Gray to BIN, Gray to
HOT, Gray to Johnson, Johnson to BIN, Johnson to Gray, Johnson
to HOT.
You can generate the module with the data width in
range from 2 to 999 (integer type). If you try to
enter values outside the range and generate the source
file, then an error dialog box will be displayed
with a report message.
When you select "one-1" option from the
"Active-HOT" list, then input code bits are active
'high'. Otherwise, input code bits are active 'low'.
You can generate priority encoding for input code bits. If
you check this check box, then the source code will check all
input bits from LSB/MSB to MSB/LSB using 'if...else...end if'
statements, and set the output. Otherwise, the input will be
checked once - all bits at the same time, using the 'case
... when' statement.
This option is available only for BIN to BCD and BCD to BIN code
converters. It allows you to convert these codes in a queue. On every
edge of CLK signal there is one BCD decade converted.
You can change MSB and LSB bit pointer for priority encoding.
HDL Code Style Description
VHDL;
Each code converter is generated using a process construct. An
active level of the EN signal is recognized
by the 'if ... end if '
instruction.
Verilog;
Each
code converter is generated using an always construct. An
active level of the EN signal is recognized
by the always block
sensitivity list. Bcd to bin converter is generated using also
function
statement.
|