4. Click on the Add Input Files icon in the Design taskbar to add the input files. This step is where you add the HDL files and constraint file (.sdc file) into Precision Synthesis' memory. For this lab, add all the files in the "Lab1" directory. (Note: there is no .sdc file for this lab). Once all the files are added, right-click on "uart_top.v" and select "Make uart_top.v Top of Design". Although the file list order is not important for implementing the design, Precision Synthesis names the logs, reports and generated netlist based on the last design file name in the list (which is assumed to be the top level of the design).

5. Notice two new icons are added to the Design taskbar, the Compile and Synthesize icons.

Compiling the design reads it into memory but does not optimize it. Compiling allows you to view RTL schematics or explicitly set constraints on the design hierarchy.

The synthesize command performs a compile if one has not already been done, and completes the optimization process. Synthesizing your design creates post synthesis netlists and reports.