8. The Schematic Viewer is invoked with the "data_en" pin selected. With the pin selected, use the RMB to issue the pop-up command, "Set Input Constraints". Set the "Input Delay" value to "0". Constraint entry requires input and output delay constraints to be relative to a clock edge. Precision Synthesis automatically determines which clock a particular port is relative to.

9. Once the constraint has been added, re-generate the missing constraints report to show that there is no unconstrained logic in the design.