Untitled Document

This lab shows you how Precision Synthesis propagates clock constraints through a Stratix PLL (phase-locked loop), emphasizing how a PLL can be used as a clock divider or multiplier.

You do not have to redefine internal clocks driven by the PLL when timing is propagated through Stratix's ALTPLL cells.


	This lab shows you how Precision Synthesis propagates clock constraints through a Stratix PLL (phase-locked loop), emphasizing how a PLL can be used as a clock divider or multiplier. You do not have to redefine internal clocks driven by the PLL when timing is propagated through Stratix's ALTPLL cells.


	Precision Synthesis allows you to view propagated clock periods in the schematic viewer, which helps you analyze designs using PLLs with complex clocking schemes. We will follow the steps outlined on this slide.