2. Next, use the Design Bar to compile the design. After the design
is compiled, use the Design Hierarchy browser to set a 5 ns clock constraint
on the ICLK pin.
Notice that even though ICLK is the input into the ALTPLL component, Precision Synthesis is able to understand this and extract it correctly into the Clocks folder.
Notice that even though ICLK is the input into the ALTPLL component, Precision Synthesis is able to understand this and extract it correctly into the Clocks folder.