3. Use the Design Bar to execute the Synthesize command.
4. After you have synthesized the design, generate a timing report. Look at the clock period. What do you notice about the clock period?
A._________________________________________
The design uses the PLL as a clock divider. It is programmed to divide the clock by 2, using the "clk0_divide_by" attribute. This results in an output clock with a period of 10 ns period.
4. After you have synthesized the design, generate a timing report. Look at the clock period. What do you notice about the clock period?
A._________________________________________
The design uses the PLL as a clock divider. It is programmed to divide the clock by 2, using the "clk0_divide_by" attribute. This results in an output clock with a period of 10 ns period.