On this slide we discuss the basic FPGA design flow.
The first step in any design is to create the RTL HDL design code.
After you've created your design, you will need to create a testbench to stimulate and test your design. The testbench consists of behavioral HDL code.
The next step is to simulate your RTL code in order to verify that the design functions correctly. This is known as RTL simulation.
Once you have simulated your design, you run the design through synthesis in order to produce a vendor-specific netlist.
After you have synthesized the design, you perform static timing analysis to make sure the design meets timing.
This netlist is read into the FPGA vendor's place and route tool, which routes the design according to vendor-specific architecture.
The final step is to perform dynamic timing analysis on the design after place and route to verify that the functionality and timing of the design has not changed.
The first step in any design is to create the RTL HDL design code.
After you've created your design, you will need to create a testbench to stimulate and test your design. The testbench consists of behavioral HDL code.
The next step is to simulate your RTL code in order to verify that the design functions correctly. This is known as RTL simulation.
Once you have simulated your design, you run the design through synthesis in order to produce a vendor-specific netlist.
After you have synthesized the design, you perform static timing analysis to make sure the design meets timing.
This netlist is read into the FPGA vendor's place and route tool, which routes the design according to vendor-specific architecture.
The final step is to perform dynamic timing analysis on the design after place and route to verify that the functionality and timing of the design has not changed.