Logic synthesis is the process of converting a logic description into a netlist of physically realizable library cells. Conventionally, it consists of a series of network transformations, decomposition and minimization of logic, followed by mapping the optimized circuit using a targeted technology library.

This approach has been the cornerstone of success using synthesis tools developed for standard cell technology. The above transformations are encompassed in two separate phases, technology independent logic optimization and technology mapping.

Logic optimization is the process of minimizing the logic representation of a circuit. Technology mapping is the process of representing the optimized circuit with the target technology resources.

Contemporary FPGA logic synthesis involves the use of technology independent optimization algorithms, followed by mapping algorithms, which realize these circuits on a given FPGA architecture.

Output from synthesis is an EDIF netlist ready for vendor place and route tools.