The following steps should be performed in order to complete
synthesis:
Step #1: Define Technology Parameters
When you set up your design in the Project Settings window, select the technology for your design from the list of device technologies. For example, you can choose Xilinx and expand the selection to choose Virtex. You select the device and speed grade from this window also.
Step #1: Define Technology Parameters
When you set up your design in the Project Settings window, select the technology for your design from the list of device technologies. For example, you can choose Xilinx and expand the selection to choose Virtex. You select the device and speed grade from this window also.
Step #2: Define Timing Constraints
Define timing constraints by doing one of the following:
Set global clock constraints and input/output delays in the Project Settings window when you set up your design from the Design toolbar. You can also set clock and pin constraints through the Design Hierarchy pane of the Design Center window after you have compiled the design. Select the clock(s) or pin(s) you want to constrain, and using the right mouse button select Set Clock Constraints or Set Pin Constraints from the pop up menu
or;
Add a constraint (SDC) file through the Project Files pane of the Design Center window. Using the left mouse button, double click on the Constraint Files icon or use the right mouse button to access the pop-up menu and select Add Constraint Files.
Define timing constraints by doing one of the following:
Set global clock constraints and input/output delays in the Project Settings window when you set up your design from the Design toolbar. You can also set clock and pin constraints through the Design Hierarchy pane of the Design Center window after you have compiled the design. Select the clock(s) or pin(s) you want to constrain, and using the right mouse button select Set Clock Constraints or Set Pin Constraints from the pop up menu
or;
Add a constraint (SDC) file through the Project Files pane of the Design Center window. Using the left mouse button, double click on the Constraint Files icon or use the right mouse button to access the pop-up menu and select Add Constraint Files.
Step #3: Perform Synthesis
During this step, the first thing the tool does is to translate synthesizable RTL HDL code into a generic gate level netlist, or technology independent gates. This involves a number of processes. During synthesis, constants are folded and propagated throughout the design, loops are unrolled, bits are minimized, and dead code, (code that is not used), is removed. During synthesis, finite state machines get optimized, and there may be other optimization algorithms performed on the code as well.
The second thing the tool does is to optimize and map the generic gate-level netlist to technology gates, utilizing any special architectural features wherever possible. This optimization can be either for area and/or speed. Precision Synthesis performs all optimizations necessary to achieve the specified results.
The final output is typically and EDIF file, which is then fed into the vendor place and route tools.
During this step, the first thing the tool does is to translate synthesizable RTL HDL code into a generic gate level netlist, or technology independent gates. This involves a number of processes. During synthesis, constants are folded and propagated throughout the design, loops are unrolled, bits are minimized, and dead code, (code that is not used), is removed. During synthesis, finite state machines get optimized, and there may be other optimization algorithms performed on the code as well.
The second thing the tool does is to optimize and map the generic gate-level netlist to technology gates, utilizing any special architectural features wherever possible. This optimization can be either for area and/or speed. Precision Synthesis performs all optimizations necessary to achieve the specified results.
The final output is typically and EDIF file, which is then fed into the vendor place and route tools.