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The first step is to set the directory for all output and implementation files.
The second step is to set the target device and frequency.

The third step is to add the VHDL, Verilog, Coregen, XDB, and EDIF files. File order does not matter. Precision Synthesis will automatically figure out file order. One exception is FPGA packages, which need to appear at the top of the list.

The fourth step is to add Synopsis Design Constraints files, or SDC files, if any.

The fifth step is to analyze, elaborate and pre-optimize. This is an optional step.

Finally, once the design is constrained, optimize and map it, and report area and timing.


	If we take a closer look at one of Precision Synthesis' task bars, the Design Task Bar, we notice that the synthesis process is now a group of push buttons. Let's go through the steps involved in performing synthesis.


	The first step is to set the directory for all output and implementation files. The second step is to set the target device and frequency. The third step is to add the VHDL, Verilog, Coregen, XDB, and EDIF files. File order does not matter. Precision Synthesis will automatically figure out file order. One exception is FPGA packages, which need to appear at the top of the list. The fourth step is to add Synopsis Design Constraints files, or SDC files, if any. The fifth step is to analyze, elaborate and pre-optimize. This is an optional step. Finally, once the design is constrained, optimize and map it, and report area and timing.