Before you run synthesis you must define design constraints. We discuss some examples of the types of constraints that you set in your design.

Since I/O pads must be added to the design prior to running Place and Route, Precision Synthesis assigns I/O pads to all ports in the top level of a design by default. Precision

Synthesis can map input buffers, output buffers, tri-state buffers, bi-directional buffers, and complex I/O registers. The I/O pads are defined in the target technology library. If the technology includes more than one I/O cell of a particular class, the technology vendor will specify a default I/O pad to use for that class of I/O pad.

Precision Synthesis allows you to override the default assignment by adding attributes to the ports or by manually instantiating the I/Os in your design. Use this method if the default I/O assignments do not meet timing, and be prepared to validate the output of the design.

Another type of constraint you can set is on pin numbers. Precision Synthesis supports assigning device pin numbers to top-level ports. These pin numbers are transferred to the synthesized netlist as a technology specific attribute, which is recognized by the place-and-route tool.

Prior to running synthesis, you can override the hierarchy control on any block in the design by placing a hierarchy attribute on a specific instance.

In order to prevent Precision Synthesis from optimizing certain blocks or instances, set the attribute (don't_touch) on that block or instance.

Precision Synthesis handles clock distribution by assigning clock buffers to top-level and internal signals that drive clock pins.

Precision Synthesis allows the user to control the fanout on data nets by overriding the library value. Do this by setting a "max_fanout" attribute on the net.

These are just a few examples of constraints and attributes you can set on your design within Precision Synthesis.