Next we talk about the most commonly used constraints. These are timing constraints.

Precision Synthesis uses clock constraints to define the timing between registers. When a clock is not defined, all combinational logic between the registers driven by the undefined clock is ignored during timing optimization.

The Clock Constraint dialog box adds a "create_clock" command to the generated .sdc constraint file.

Precision Synthesis can handle Multiple Clocks in your design. If different clocks propagate to the source and destination registers, constraints can still be checked if the clocks are synchronous.

Clocks can differ in phase. They are modeled as a latency adjustment.

Clocks can differ in frequency, which requires the "closest approach of edges" to be used for analysis.

Clocks that are asynchronous are said to be in different domains. SDC does not support the concept of clock domains. However, Precision Synthesis has added a switch to the create_clock command to model this behavior. The command is:

create_clock -period <value> -name <value> -domain <domain_name>