We continue our discussion about timing constraints in Precision
Synthesis with input and output constraints.
If a signal is set with an input delay, it means the signal
will "arrive" X ns after the rising clock edge, and so we must
specify a rising clock edge.
create_clock clk1
–period 10
set_input_delay 4 load -clock clk1
If a signal is set with an output delay, it means the output
of the signal must be valid after the rising clock edge.
create_clock
clk –period 10
set_output_delay 7 out1 -clock clk1