Timing optimization focuses its efforts on paths in the design that violate timing constraints. For example, if a path is seen as violating, but is in fact not a problem, the optimizer will waste time trying to fix the false violation. It will likely insert unnecessary circuitry, and may cause real violations to go unfixed. False path definitions are used in this case to avoid the violation.

False paths occur for a variety of reasons. A path may be false because the circuitry involved operates slower than your constraints indicate. For example, test logic can be operated at a slower frequency. Paths from master reset signals are often false for similar reasons. Often reset sequences occur over many clocks, and it does not matter exactly when a particular register is reset.

Another possible reason for using a false path definition is to exclude paths that exist in the circuit, but never interact. The static analysis tool does not know the relationships of the states of your circuit, so false paths are used to help eliminate paths that will never occur because of the operation of the system. Finally, false paths may be identified as overly pessimistic because of the static analysis approach.

Multi-cycle path definitions instruct the analysis tool to check constraints at the destination register at a clock edge later than normal.

For setup, one clock is the default. For hold, zero clocks are the default.
If you specify only from, through or to, you have defined a single point path.
This type of constraint is used to "relax" timing constraints on specified logic and it can be applied "to", "from" or "through" any node in any combination.