The compile command has no arguments or switches. It will read and compile all the input files, but it does not perform synthesis.

You must compile your design before you set individual port constraints using the command line, constraint editor or in a Tcl file. The design must be compiled into memory before you can view the RTL schematics.

Also, during compilation a syntax and synthesis construct check is performed on the RTL design. If errors are found, you must correct them and recompile your design.