Precision Synthesis allows you to adjust the register timing for the Virtex family. This process is called register retiming. Observe the diagram above. The left-hand side of the diagram has 3-levels of logic (this represents retiming off), but on the right hand side the registers are moved forward and logic is reduced to only one level (this represents retiming on). Retiming the circuit may cause the design to meet timing. Register retiming is off by default. Enable it through the Tools menu option by selecting Tools > Set Options. When the Synthesis Options window loads, select "Optimization" on the left and "Retiming" on the right.