Next we discuss how to infer RAM in the Altera Stratix chip.

Stratix RAM must be synchronous, although pseudo-asynchronous reading is possible.

RAMs are best implemented using arrays, as case statements do not infer RAM (they usually infer MUXes). Case statements can be used for ROMs, however.

Precision Synthesis detects a RAM or a ROM from the style of the RTL code at a technology-independent level, then maps the element to a generic LPM module in the in-memory RTL database at compile time. If RAM is detected, the element is mapped to a RAM_DQ or RAM_IO module.

If ROM is detected, it is mapped to a LPM ROM module. During the technology-mapping phase of synthesis, Precision synthesis maps the generic LPM module to the equivalent Altera LPM cell.

Shown here is a Verilog example of a simple dual-port RAM. As previously stated, RAM inference is automatically controlled by the software. However, you may include in your code an attribute that would target the memory for any of the RAM Block Sizes within the Stratix device. This example targets the M4K RAM block.