The example on this slide illustrates how the Precision Synthesis GUI allows you to assign a LogicLock region to a block in the compiled design.

Any hierarchical block can be "LogicLocked". What does "LogicLocked" mean? The Stratix architecture has been optimized for true block-based design. Quartus II supports a LogicLocked block-based design flow that enables you to assign blocks of logic to regions on a device. Precision Synthesis attaches a LogicLock attribute to the block that is passed to Quartus II as a property in the EDIF netlist.

With the combination of the high performance Stratix architecture and the ease-of-use of LogicLock, customers can get much higher performance and dramatically reduce their development time.