Now we discuss the LogicLock design flow. Within Precision Synthesis, the LogicLock attribute is applied to a block in the design. The design is then synthesized. The output may consist of multiple EDIF and Tcl files.
 
 
Within Quartus II the design is elaborated and analyzed, and the LogicLock blocks are imported. The design is compiled with the LogicLock constraints back-annotated to the design. The designer may make incremental changes to the design, and re-import blocks as needed. The design is then re-compiled. This flow is followed until the designer is satisfied with the final product.