12.0 Continuous Assignments

13.0 Task Definitions

14.0 Function Definitions

15.0 Specify Blocks

15.1 Specparam Declarations

Timing constraint checks are system tasks that model restrictions on input changes, such as setup times and hold times.

15.3 Pin-to-pin Path Delays

if (first_condition) simple_or_edge-sensitive_path_delay
if (next_condition) simple_or_edge-sensitive_path_delay
ifnone simple_path_delay

specparam t1 = 3:4:6,
          t2 = 2:3:4;
(a => y) = (t1,t2);

if (opcode = 3'b000)
       (a,b *> o) = 15;
if (opcode = 3'b001)
       (a,b *> o) = 25;
ifnone (a,b *> o) = 10;

primitive primitive_name (output, input, input, ... );
  output terminal_declaration;
  input terminal_declaration;
  reg output_terminal;
  initial output_terminal = logic_value;
  table
    table_entry;
    table_entry;
  endtable
endprimitive

User Defined Primitives define new primitives, which are used exactly the same as built-in primitives.

	All terminals must be scalar (1-bit).
	Only one output is allowed, which must be the first terminal.
	The maximum number of inputs is at least 9 inputs for a sequential UDP and 10 inputs for a combinational UDP.
	Logic levels of 0, 1, X and transitions between those values may be represented in the table. The logic value Z is not supported with UDPs.
	reg declaration (optional) defines a sequential UDP by creating internal storage. Only the output may be a reg.
	initial (optional) is used to define the initial (power-up) state for sequential UDP's. Only the logic values 0, 1, and X may be used. The default state is X.

16.1 UDP Table Entries

input_logic_values : output_logic_value ;

Combinational logic table entry. Only logic level values may be specified (0, 1, X and don't care).

input_logic_values : previous_state : output_logic_value ;

Sequential logic table entry. May only be used when the output is also declared as a reg data type. Both input logic level and input logic transition values may be specified.

	A white space must separate each input value in the table.
	The input values in the table must be listed in the same order as the terminal list in the primitive statement.
	Any combination of input values not specified in the table will result in a logic X (unknown) value on the output.
	Only one signal may have an edge transition specified for each entry in the table.
	If an edge transition is specified for one input, the UDP becomes sensitive to transitions on all inputs. Therefore, all other inputs must have table entries to cover transitions, or when the transition occurs the UDP will output an X.
	Level sensitive table entries have precedence over edge sensitive table entries.

16.2 UDP Table Symbols

primitive mux (y, a, b, sel); //COMBINATIONAL UDP
  output y;
  input sel, a, b;
  table  //table order for inputs matches primitive statement
  // a  b  sel : y
     0  ?   0  : 0;  //select a; don't care about b
     1  ?   0  : 1;  //select a; don't care about b
     ?  0   1  : 0;  //select b; don't care about a
     ?  1   1  : 1;  //select b; don't care about a
  endtable
endprimitive

primitive dff (q,d,clk,rst); //SEQUENTIAL UDP
  output q;
  input clk, rst, d;
  reg q; //declaring output as reg defines
         //sequential device with an internal
         //storage state
  initial q = 0; //powers up in reset state
  table
  // d  clk rst:state:q
     ?   ?   0 :  ?  :0; //low true reset
     0   R   1 :  ?  :0; //clock in a 0
     1   R   1 :  ?  :1: //clock in a 1
     ?   N   1 :  ?  :-; //ignore negedge of clk
     *   ?   1 :  ?  :-; //ignore all edges on d
     ?   ?   P :  ?  :-; //ignore posedge of rst
     0 (0X)  1 :  0  :-; //reduce pessimism
     1 (0X)  1 :  1  :-; //reduce pessimism
    endtable
 endprimitive

Following is a list of Verilog HDL constructs supported by most synthesis tools.

	This list is not specific to any one tool - each synthesis tool supports a unique subset of the Verilog language.
	The constructs listed in this section represent a subset of the Verilog HDL that are supported by most synthesis tools.
	Verilog constructs not listed in this section may be supported by some synthesis tools - refer to the specific synthesis tool documentation.

Verilog HDL Constructs	Notes
module declarations	both module and macromodule keywords fully supported
port declarations input output inout	fully supported; any vector size supported
net data types wire wand wor supply0 supply1	scalars and vectors fully supported
register data types reg integer	register variables: may be scalar or vector or register array may be restricted to only making assignments to a register from just one procedure integers default to 32 bits
parameter constants	limited to integers; parameter redefinition may not be supported
module instances	fully supported; both port order and port name instantiation supported
primitive instances and nand or nor xor buf not bufif1 bufif0 notif1 notif0	only gate primitives are supported
assign continuous assignment	fully supported; both explicit and implicit forms supported
function definitions	may only use supported constructs; must be defined before being referenced
task definitions	may only use supported constructs; must be defined before being referenced
always procedural block	must have a sensitivity list
begin--end statement groups	fully supported; named and unnamed blocks supported
disable statement group	must be used within the same named block that is being disabled
= blocking procedural assignment <= non-blocking procedural assignment	fully supported; may be restricted to using only one type of assignment for all assignments to the same register variable
assign procedural continuous assignment	fully supported; the deassign keyword may not be supported
integer values	fully supported; all sizes and bases
if if-else case casex casez decision statements	logic X and Z only supported as don't care bits
for loops	the step assignment must be an increment or decrement (+ -)
while loops forever loops	loop must take one clock cycle for each loop cycle (i.e.: an @(posedge clk) or @(negedge clk) must be within the loop)
operators & ~& | ~| ^ ^~ ~^ == != < > <= => ! && || << >> {} {{}} ?: + - * /	operands may be: scalar or vector constant or variable The divisor for divide operator may be restricted to constants and a power of 2 the === and !== operators are not supported
vector bit selects vector part selects	fully supported on the right-hand side of an assignment; restricted to constant bit or part selects on the left-hand side of an assignment

EDA tool vendors and tool users may define tasks and functions specific to their tool, such as text output or waveform displays.

	System tasks and functions begin with the $ (dollar sign).
	Users may define additional built-in tasks and functions using the Verilog Programming Language Interface (PLI).
	A few of the most common system tasks and functions are listed in this section.

$monitor("text_with_format_specifiers", signal, signal, ... );

Invokes a background process that continuously monitors the signals listed, and prints the formatted message whenever one of the signals changes. A newline is automatically added to the text printed.

$display("text_with_format_specifiers", signal, signal, ... );

Prints the formatted message once when the statement is executed during simulation. A newline is automatically added to the text printed.

$write("text_with_format_specifiers", signal, signal, ... );

Like $display statement, except that no newline is added.

$strobe("text_with_format_specifiers", signal, signal, ... );

Like the $display statement, except that the printing of the text is delayed until all simulation events in the current time step have executed.

mcd = $fopen("file_name");

A function that opens a disk file for writing, and returns a 32-bit integer multi-channel-descriptor (mcd) pointer to the file.

$fclose(mcd);

A function that closes a disk file that was opened by $fopen.

$monitor(mcd, "text_with_format_specifiers", signal, signal, ... );
$display(mcd, "text_with_format_specifiers", signal, signal, ... );
$write(mcd, "text_with_format_specifiers", signal, signal, ... );
$strobe(mcd, "text_with_format_specifiers", signal, signal, ... );

Variations of the text display tasks that write to files which have been opened with $fopen.

$time

Returns the current simulation time as a 64-bit integer.

$stime

Returns the lower 32-bits of simulation time as an integer.

$realtime

Returns the current simulation time as a real number.

$timeformat(unit, precision, "suffix", min_field_width);

Controls the format used by the %t text format specifier.

	unit is the base that time is to be displayed in, from 0 to -15
	precision is the number of decimal points to display.
	suffix is a string appended to the time, such as " ns".
	min_field_width is the minimum number of characters that will be displayed.

  0 =   1 sec
 -1 = 100 ms
 -2 =  10 ms
 -3 =   1 ms 

 
 -4 = 100 us
 -5 =  10 us
 -6 =   1 us 

 
 -7 = 100 ns
 -8 =  10 ns
 -9 =   1 ns 

 
-10 = 100 ps
-11 =  10 ps
-12 =   1 ps 

 
-13 = 100 fs
-14 =  10 fs
-15 =   1 fs 

Example: $timeformat(-9, 2, " ns", 10);

Compiler directives provide a method for EDA tool vendors to control how their tool will interpret Verilog HDL models.

	Compiler directives begin with the grave accent character ( ` ).
	Compiler directives are not Verilog HDL statements; there is no semi-colon at the end of compiler directives.
	Compiler directives are not bound by modules or by files. When a tool encounters a compiler directive, the directive remains in effect until another compiler directive either modifies it or turns it off.
	A few of the most common compiler directives are listed in this section.

`reset_all

Resets all compiler directives that have a default back to the default. Directives that have no default are not affected.

`timescale time_unit base / precision base

Specifies the time units and precision for delays:

	time_unit is the amount of time a delay of 1 represents. The time unit must be 1 10 or 100
	base is the time base for each unit, ranging from seconds to femtoseconds, and must be: s ms us ns ps or fs
	precision and base represent how many decimal points of precision to use relative to the time units.

Example: `timescale 1 ns / 10 ps
Indicates delays are in 1 nanosecond units with 2 decimal points of precision (10 ps is .01 ns).

Note: There is no default timescale in Verilog; delays are simply relative numbers
  until a timescale directive declares the units and base the numbers represent.

`define macro_name text_string
`define macro_name (arguments) text_string (arguments)

Text substitution macro. Allows a text string to be defined as a macro name.

	text_string will be substituted in place of the macro_name where ever the macro name is used.
	text_string is terminated by a carriage return. The string must be on one line.
	arguments are evaluated before text is substituted.
	macro_name must also be preceded by the grave accent mark ( ` ) each time the macro name is used.
	Comments may be used. They are not substituted into the place of the macro name.

Examples:

   `define cycle 20 //clock period
   always #(`cycle/2) clk = ~clk;

   `define NAND(dval) nand #(dval)
   `NAND(3) i1 (y,a,b);
   `NAND(3:4:5) i2 (o,c,d);

`include "file_name"

File inclusion. The contents of another Verilog HDL source file is inserted where the `include directive appears.

`ifdef macro_name
     verilog_source_code
`else
     verilog_source_code
`endif

Conditional compilation. Allows Verilog source code to be optionally included, based on whether or not macro_name has been defined using `define or an invocation option.

Examples:

   `ifdef RTL
      wire y = a & b;
   `else
      and #1 (y,a,b);
   `endif

`celldefine
`endcelldefine

Flags the Verilog source code between the two directives as a cell. Some tools, such as a delay calculator for an ASIC design, need to distinguish between a module that represents an ASIC cell and other modules in the design.

`default_nettype net_data_type

Changes the net data type to be used for implicit net declarations. Any of the net data types may be specified. By default, the implicit net data type is wire.

`unconnected_drive pull1
`unconnected_drive pull0
`nounconnected_drive

Determines what logic value will be applied to unconnected module inputs. The default is `nounconnected_drive, which floats unconnected inputs and nets to high impedance.

`delay_mode_zero
`delay_mode_unit
`delay_mode_path
`delay_mode_distributed

Specifies the simulation delay mode.

`uselib file=file dir=directory libext=extension

Specifies the Verilog source library file or directory in which the compiler should search for the definitions of modules or UDPs instantiated in a design. A `uselib directive with no arguments removes any preceding library search directives.

Examples:

   `uselib file=/models/rtl_lib
      ALU i1 (y1,a,b,op);   //RTL model
   `uselib dir=/models/gate_lib libext=.v
      ALU i2 (y2,a,b,op);   //Gate model
   `uselib   //turn off `uselib searching

 

online Verilog HDL Quick Reference Guide
by Stuart Sutherland of Sutherland HDL, Inc. - Portland, Oregon, USA

copyrighted material - do not reproduce any portion by any means
professionally printed reference guides are available - see www.sutherland.com for details