Signals vs Variables (Cont.)

VHDL Objects

Signals vs Variables (cont. 2)

This composite table of results clearly shows the differences between variables and signals

signals variables

Time | a b c | out_1 out_2 | out_3 out_4

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0 | 0 1 1 | 1 0 | 1 0

1 | 1 1 1 | 1 0 | 0 1

1+d | 1 1 1 | 0 0 |

1+2d | 1 1 1 | 0 1 |
The statements produce the same end result