| ASIC | Application Specific Integrated Circuit. A chip which is custom designed for a specific use and purpose. |
| ASSP | Application Specific Standard Product. A chip designed for a specific application but meant for use in multiple applications. |
| BGA | Ball Grid Array. A surface-mount packing technique. |
| BIST | Built-in-Self-Test. Usually for testing memories and other regular structures |
| BitGen | The command-line used for configuration step performed by Xilinx ISE |
| Bitstream | A bitstream is used to program an FPGA device. It contains information to configure the FPGA routing and logic resources as designed by designer. |
| Block RAM | A block of random-access memory built into the device, as distinguished from distributed, LUT-based random-access memory. |
| BUFGCE | A Xilinx® primitive which is basically used for clock management. Global clock buffer is gated with a clock-enable signal. If clock enable is disabled the clock will also be disabled. |
| BUFGMUX | Used to switch between clocks without glitches. |
| Carry logic | Mainly used to implement arithmetic logic functions and exists in each slide and runs along each column of CLBs as well as the top and bottom CLBs. |
| Certify® | Name of the Synopsys FPGA-based prototyping and partitioning software tools. |
| ChipScope™ | ChipScope is the integrated logic analyzer add-on to the Xilinx® ISE® software. |
| Core | A colloquial name for a complex block of IP. |
| DCM | Digital Clock Manager. A design element which provides multiple functions. It can implement a clock-delay locked loop, a digital frequency synthesizer, digital phase shifter, and a digital spread spectrum. |
| DDR | Double Data Rate uses both edges of a clock to capture data. |
| EDIF | Electronic Design Interchange Format. An industry-standard netlist format. |
| Footprint | The shape, pin names, and functionality of a library macro or component. |
| Foundry | A silicon wafer fabrication facility which offers production services to other parties. |
| Gate Array | An early and still common form of ASIC chip. This requires the use of bespoke masks for the last few stages of chip fabrication to be tailored to a specific design. |
| Global Buffers | Low-skew, high-speed buffers that drive large fanout signals, usually clocks, across an FPGA. |
| HDL | Hardware Description Language. A language used for modeling designing and simulating hardware. The two most common HDL languages are VHDL and Verilog. |
| IO blocks | The input/output logic of the device containing pin drivers, registers and latches, and 3-state control. |
| IO pads | Input/output pads that interface the silicon device with the pins of the device package. |
| IBUF | A circuit which acts as a protection for the chip, shielding it from eventual current overflows. |
| ICE | In-circuit Emulation. |
| ISE® | Integrated Software Environment, the overall name for Xilinx® FPGA tools, including project management, place & route, bitstream generation and debug. Pronounced as ‘ice’ |
| ISERDES | Input Serializer/Deserializer. A dedicated source synchronous IO architecture. |
| JTAG | Joint Test Action group is an IEEE 1149.1 standard test access port and boundary scan architecture. |
| LOC | Location constraint. Used to lock pin locations or to place logic in specific locations in the FPGA. |
| LVDS | Low Voltage Differential Signaling. Differential signaling is a method of transmitting information electrically by means of two complementary signals sent on two separate wires. This offers better immunity to ambient noise and faster signal propagation. |
| Macro (1) | A slightly out-of-date term for a component made of nets and primitives, FFs, or latches that implement mid-level functions, such as add, increment and divide. Soft macros and relationally placed macros (RPMs) are types of macros. |
| Macro (2) | A universal control embedded into the RTL and visible from any point during compilation. Often defined in Verilog using define command. |
| MMCM | Mixed-Mode Clock Manager. Multi-output configurable block which includes PLL and phase shifters to give fine-grain control of clocks within a Xilinx® FPGA. |
| NCD | A Native Generic Database file describes the logical design reduced to Xilinx® primitives. |
| Netlist | A text description of the circuit connectivity. It is basically a list of connectors, a list of instances, and, for each instance, a list of the signals connected to the instance terminals. In addition, the netlist contains attribute information. |
| Pad-to-pad delay | A combinatorial path which starts at an input of the chip and ends at an output of the chip. The pad-to-pad path time is the maximum time required for the data to enter the chip, travel through logic and routing, and leave the chip. It is not controlled or affected by any clock signal. |
| PCIe | Peripheral Component Interconnect - Express: An international standard for fast serial interconnection. |
| Pin locking | Process by which a signal is given a location on a specific FPGA package pin. |
| Place & route | Two major processes involved in back-end tools deciding which resources on an FPGA will be used to implement each part of the netlist. and then routing the signals between them. |
| PLL | Phase locked Loop is an analog clock-locking circuit. Compares two clock signals and aligns the two. Used for synchronizing and zero-delay buffering plus division and multiplication of frequency. |
| Primitives | The most fundamental design elements in the Xilinx® libraries, sometimes referred to as BELs, or Basic Elements. Primitives are the design element “atoms” and can be combined to create macros. Examples of Xilinx® primitives are the simple buffer, BUF, and the D FF with clock enable and clear, FDCE. |
| RLOC | Relative Location Constraints . Used to group logic elements together to reduce routing delays in the design. Logic elements with RLOC can be moved but must maintain the same relative placement. This prevents routing delays appearing between the elements. RLOCs are used to create (relatively placed macros (RPMs). |
| RTL | The short name given to hardware description code written at the Register Transfer Level, rather than at a system level or gate level. Often used colloquially to denote the source for a design. |
| Skew | Delay introduced differentially into one signal with respect to another. |
| TRACE | The Timing Reporter And Circuit Evaluator. A command-line utility for performing static timing analysis of a design based on input timing constraints. |
| UCF | User Constraints File. A format for feeding constraints and other controls into the Xilinx® ISE® tools. |