Introduction to High-Density Programmable Design (2/4)...


Introduction to High-Density Programmable Design
By Lee Hansen and Anil Telikepalli, EEdesign
Feb 6, 2001 (9:43 AM)

Part 2 of 4
By Lee Hansen, Xilinx Software Product Marketing Manager and Anil Telikepalli, Xilinx Senior Technical Marketing Engineer

In Review
In Part 1 of this four-part series on high-density programmable logic design, we focused on partitioning the overall design and getting prepared for design entry. Using Xilinx High-Level Floorplanner we have a high-density device partitioned into manageable modules based on entry method and keeping timing concerns and signal traffic to a minimum. Coupled with Xilinx Modular Design each module can be designed and implemented independently, delivering device completion in faster. In this article we?l explore design entry and management and the various methods available to quick and accurate design creation. Most important, we'll explore the exploding use of intellectual property, or IP, as a design solution.

Design Creation
The most common method of design creation today is either VHDL or Verilog language text entry through a standard text editor, or the now widespread use of context-sensitive language editors and LEDATM verification. These editors can complete language statements through simple keystrokes, analyze syntax for missing language structures, and in general provide a very good editing environment. Xilinx Project Navigator (Figure 1), where the engineer drives design entry, contains a complete VHDL/Verilog language-editing environment, with context-sensitive help, and language templates to help the user create code fast.

Figure 1 - Xilinx Proj

The use of schematic entry for design module creation is rapidly waning for high-density design work. The amount of effort required during schematic entry is just too intensive and time-consuming and too prone to error. But especially at the top level of the design, schematic entry is still a quick and easy way to place small amounts of necessary glue logic. Graphic entry as a design method is experiencing a resurgence in high-density design. In the late 1980s graphic entry became a popular design method, but as device density grew it proved to be too cumbersome. Coupled with the use of Xilinx Modular Design, graphic entry is making a strong comeback as design work concentrates on implementation of smaller modules, not the overall device. With Xilinx's recent purchase of Visual Software Solutions, StateCAD and HDL Bencher are now being tightly integrated into the Xilinx standard design tools. StateCAD offers state-diagram, finite state machine, truth table, and flow-chart logic entry that can then be output as VHDL or Verilog code. These graphic-entry methods offer very good documentation style in a very readable and easily understood format, and are the preferred method of entry for a growing number of design engineers, depending on the size of the target module.

The Focus on IP
The fastest growing design option of choice for high-density device work is by far IP. This includes free or purchased off-the-shelf cores and reuse of internally captured and verified code. The manager staring down a project completion deadline is looking for quick, accurate, affordable answers that can be tuned to a given use. The very nature of the FPGA device fabric allows IP to enable quick product turnaround in a reliable, repeatable format. Programmable IP core has already been verified against the device family, eliminating the need for silicon verification and thus reducing overall design time. Add to that the large-scale availability of fully verified complex cores, and the design manager now has a wide variety of design solutions at hand. This frees team members to concentrate on other critical design areas toward completion. Using IP in high-density FPGAs is not accomplished just with cores targeted at different applications, though how can those solutions best be delivered to the design? Xilinx CORE Generator (Figure 2) is provided as part of the standard Xilinx software tool suite, and is linked with regular core updates available via the Xilinx IP Center. Cores are offered to the designer in a library interface. The designer can choose the parameters to customize the core and make the area-speed trade-offs for that specific design.

Figure 2 - Xilinx core generator

IP Internet Capture is integrated into Core Generator to facilitate design reuse. Customers can capture their corporate-developed IP as standardized cores and use the CORE Generator as a cataloging and delivery vehicle. Customer cores then appear in the library interface for later selection and use. Through the LogiCore program, Xilinx offers hundreds of standard IP functions. These include cores such as multipliers, filters, FIFOs, error correction, Ethernet MACs, ATM functions, HDLC controllers and video blocks among many others. The AllianceCORE program expands this offering to include some of the best third party IP available. And the Reference Design program offers free advice and design applications from certified design centers throughout the world. Xilinx has wrapped this information together at the Xilinx IP Center ( containing everything you need to design with IP.

High-Density Applications
Dropping in a core to solve a critical function is great, but only a part of the overall solution. As devices migrate to higher densities a key function that FPGAs perform on the board is as connectivity vehicles, interfacing the internal custom logic implemented in the FPGA to external systems such as memories, network fabric, PC peripherals and other ASSPs, and in this arena programmable IP serves a vital function. To meet their needs, engineers use PCI, PCI-X, Rapid IO, POS-PHY, Flexbus, SDRAM controllers, Utopia and other high-performance cores. Your designers don? need to spend time recreating common interface functions, or worry about spending time translating bus logic. For DSP design work, FPGAs offer superior DSP processing power compared to any mainstream digital signal processor. Xilinx has launched the XtremeDSP initiative to facilitate the efficient use of programmable logic for system designers. Cores such as advanced DSP filters, Reed-Solomon filters, modulators, transforms, math building blocks, video and imaging algorithms and wireless cores are all available today. And through XtremeDSP, Mathworks and Xilinx provide seamlessly integrated MATLAB/Simulink and System Generator software, bridging the gap between the system design domain and direct implementation in the FPGA.

Design Management
While we're now able to choose from several diverse design methods, management of the creation process is a critical piece to smooth completion. Xilinx Project Navigator (Figure 1) is also an intelligent design manager making design entry and implementation much easier to deal with. Project Navigator launches the correct tool for a given process and tracks that module during creation and through implementation. Context-sensitive flows are available as pushbutton processes to correctly implement a module. The user can easily see what processes are completed or next in line to execute. Snapshots can be taken to enable revision control of the design and can then easily be restored at any point, leaving the engineer to pursue different design ideas and abandon them if need be. Feedback along the bottom window is Web-enabled so that error messages can be passed to the Xilinx Solution Center where solutions are kept constantly up to date, giving the most direct and accurate answers to the engineer, eliminating the time spent browsing through help files and documentation to find the correct answer.

Coming Up
We've looked at planning and managing the overall device, now we've looked at how to implement the design on a module-by-module basis. We're coming to where the rubber meets the road; next time we'll look at synthesis and verification. Go to for more information on the products mentioned here including the Xilinx IP Center.


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