Introduction to High-Density Programmable Design (3/4)...


Introduction to High-Density Programmable Design: Part 3 of 4
By Lee Hansen, Xilinx Software Product Marketing Manager, EEdesign
Mar 23, 2001 (7:19 AM)

In Review
In Part 1 of this four-part series on high-density programmable logic design, we focused on partitioning the overall design and getting prepared for design entry. Using Xilinx High-Level Floor planner, we have a high-density device partitioned into manageable modules based on entry method, timing concerns and keeping anticipated signal delays to a minimum.

In Part 2 we looked at high-density design capture, both language-based and various graphical capture methods. We discussed the concerns surrounding the selection and use of the rapidly growing area of Intellectual Property to fulfill design needs.

In this article we?l explore implementation: place and route, timing constraints and synthesis. Also, we will examine how to get the design from concept through capture and onto the device, and the special problems high-density designs bring to the implementation stage. Implementation is where the rubber meets the road for all logic design work--the best design is useless if it can? be programmed onto the FPGA, and the most advanced FPGA offers the user no advantage if its features can? be programmed. Implementation is the domain where design and device merge.

Modular Design
Before we leap into implementation, refer back to Article 1 and how we attacked this high-density project by first partitioning our device into modules. These modules are now being realized separately. Since we?e started with that floor plan, we can now leverage a new technology, Xilinx Modular Design, that was pioneered by Xilinx to make high-density design even faster.

Xilinx Modular Design is a productivity option that works in addition to the ISE design software. With it, all Xilinx implementation tools can be used independently and completely on each module of the design, enabling design teams to work in parallel to complete their individual modules. And once a module is complete those synthesis and routing results are locked in place according to the device floor plan. If one module must change, the surrounding modules all remain locked with their results and timing guaranteed.

Modular Design delivers speed and productivity in high-density designs by offering a true team design environment that allows parallel implementation of the partitioned design modules. But more important, Modular Design treats each module as a separate design by completing and then locking down implementation results on a module-by-module basis. A change to one module does not affect the implementation or timing of completed modules. High-density designs are finished much faster than in a traditional serial design flow.

Timing Constraints
As we're accelerating device completion by working on smaller design modules, and as each of those modules can be implemented separately, most of the discussion around timing constraints for synthesis is very similar to general synthesis rules for small to medium designs. However, there are a few key factors worth repeating that will affect high-density implementation results.

Don't over-constrain. Many designers operate under the mistaken belief that over-constraining a module will guarantee timing. But it can force the synthesis tool to introduce extra gates into the finished module, a crucial mistake in high-density design work. One technique you can consider is to begin implementation by synthesizing without timing constraints. Let the synthesis tool work for the best design and point out the areas that will cause problems, then go back and work to constrain only those portions of the module.

Timing can also be seriously affected by the "synthesizability" of the design code. In December, Xilinx announced the 1.0 coding style guide for the Synopsys LEDA tool language checkers. The LEDA set of tools can verify your module against standard good-coding practices. This reduces the chances that problems will crop up during implementation because of bad coding styles, like introducing unnecessary latches into the finished module that cause timing analysis mistakes. And LEDA tools are also flexible for customized coding styles to be programmed, to assure that your design meets your own specific corporate coding standards.

Physical Synthesis
The two most time-intensive steps in implementation are place and route and synthesis. These two critical design phases are loops of multiple iteration where the designer spends most of the design effort attempting to close timing requirements for a module. A good deal of time can be spent running synthesis to the point where timing estimates come close to expectations, then place and route is run to lock down that synthesis run so that timing can be accurately verified to make sure design goals have actually been achieved. More often than not the design must be tweaked and re-tweaked with either synthesis or place and route or both having to be run over and over before design goals are finally met. This has been the standard implementation flow in logic design for years.

Xilinx has pioneered a new technology for programmable logic to help shorten the design cycle. Physical synthesis between Xilinx ISE software and its synthesis partners makes the implementation loop much more intelligent. In physical synthesis, the synthesis step now has knowledge of the floor plan, the physical device configuration and early placement knowledge, and can thus make decisions to help speed the overall design results. Place and route can also pass timing information back to the synthesis tool once critical delays have been identified. The number of iterations seen by the engineer using traditional implementation methods is reduced and device performance is increased.

Physical synthesis for Xilinx design flows works with its place-and-route tools and its synthesis partner tools with Synplicity and Exemplar and Xilinx' own synthesis software, XST, for Xilinx Synthesis Technology.

Meeting Timing Requirements
High-density design implies squeezing as much into the device and, consequently, the module as is physically possible. This simultaneously pushes the envelope of device performance and clock speeds. If you've tweaked and re-tweaked using all the implementation tools at your disposal and you're still not meeting device performance, are you stuck at retargeting to a higher performance device? Not necessarily.

Xilinx includes XST in the ISE development product kits. It focuses on optimizing Xilinx programmable device technology and implementation barriers and passing those technology solutions onto the company's synthesis partnerships with Synplicity, Synopsys and Exemplar.

If you're running just below the edge of your performance requirement try running an implementation pass through XST. If you get better speeds, you may have saved several passes of circuit tuning; if not, you've only lost the one synthesis pass.

Coming Up
In the conclusion of this series next month we discuss verification and reprogrammability. Go to for more information on Xilinx ISE software capabilities.


Copyright 2002 © CMP Media, LLC

  Send to a colleague | Print this document