to High-Density Programmable Design
By Lee Hansen, Xilinx Software
Product Marketing Manager, EEdesign
May 8, 2001 (10:02 AM)
In Parts 1 through 3 of this series on High-Density Programmable logic
design, we used Xilinx High-Level Floorplanner to partition a high-density
target device into manageable design modules based upon entry method, and
keeping anticipated signal delays to a minimum. We then discussed design
capture, both language-based and graphical capture methods. We then talked about
the issues surrounding the selection and use of the rapidly growing area of
Intellectual Property to fulfill design needs. We then moved on to high-density
implementation: place & route, timing constraints and synthesis.
Throughout this series of articles Xilinx Modular Design has allowed us to
implement each design module of the high-density device independently, we will
now extend this streamlined design flow to verification. And then as each module
is completed, the results will be locked in place while we wait for all modules
to be completed by the other design teams. Xilinx Internet Team Design (ITD) is
an optional product that can further enhance our modular design flow. ITD allows
the team design flow we've been using to be driven and statused via the
corporate intranet on the engineering manager's preferred internet browser. ITD
optionally allows implementation and now verification to be driven from standard
scripts to assure all design flow steps have been completed, and to guarantee
results and repeatability.
We're now ready to wrap up this series on high-density programmable logic by
launching into verification. What are the different verification options
available at the different stages of module design, and once we bring the
modules together into the finished device, how can we continue verification at
the device level?
HDL simulation offers a solid verification method for the design modules.
Through the flexibility of HDL simulation and integration with the
implementation tools, each module can be verified at differing stages of design
work; during HDL creation, and after synthesis to check design functionality,
and again after place & route using back-annotated device path delays. This
multi-stage verification strategy offers a “checkpoint?at each major stage of
Xilinx ISE Foundation software includes a version of the well-known Modelsim
family of HDL simulators offered from Model Technologies. Modelsim offers the
speed and ease-of-use needed for high-density design simulation. ISE also
supports integration for the various HDL simulators found in the majority of EDA
Test vectors must be generated for each module under design, a task that
rapidly expands as designs become larger; particularly if HDL simulation is used
to verify the overall device. Xilinx now offers HDL Bencher as part of the ISE
design suite of software. With HDL Bencher a testbench for a design module can
be quickly and easily captured early in the design process. HDL Bencher does not
require the engineer to spend time generating test vectors or to be savvy at
scripting, since the graphic interface supports quick extraction of a test suite
at the beginner or at the expert level.
HDL Bencher enhances the checkpoint verification strategy operating as a
“known-good?evaluation criteria that tracks each module during design.
Design module to chip verification
We are now at the crossroads where we're finishing module design and
verification, and then moving onto design verification for the overall device.
HDL Simulation is an example of a verification option that works at the module
level, and can also be used for the overall device. However, High-density design
requirements are driving the use of both existing and new verification
Static Timing Analysis
Static timing analysis (STA) is now well established as a chip design
checkpoint, and has been considered the "sign-off" level timing verification for
FPGAs for several years. Xilinx Static Timing Analysis is delivered as part of
ISE and can be easily used as your final programmable device checkpoint. With
the upcoming version 4.1i of ISE software, designers will also have the option
of starting to use Synopsys PrimeTimeTM in their FPGA verification work.
A STAMP model can also be written out for any finished Xilinx high-density
device. STAMP models let you integrate FPGA pin-to-pin delays into system level
PC board tools, so the FPGA is represented during overall system level analysis.
In the upcoming version 4.1i of Xilinx software, formal verification
technologies from Synopsys and Verplex will be supported. Formal verification is
a unique new technology brought about by the transition into ever-higher density
design projects. As the gate counts of completed designs have grown; the need
for test vectors has grown accordingly at a geometric rate. When considering the
number of vectors that must be written and then read for a 64-bit bus converter
design to ensure a thorough test of functionality, you can see that device
verification becomes daunting. This has led to the growth of formal verification
strategies for large-scale programmable designs.
In the “equivalence checking?version of formal verification, mathematical
algorithms are used to verify the logic at each phase of the design against the
pre-synthesis version. By comparing blocks of logic, equivalence checkers can
compare designs in a matter of minutes, vs. hours or days using traditional
gate-level simulation techniques. Whenever a new stage of the design flow has
been completed, the equivalence checker can be run quickly and efficiently to
verify the design is still accurate.
Verification in the system
Xilinx has created a solution that integrates verification onto the silicon
itself. ChipScope Software combined with the Integrated Logic Analysis (ILA)
core allows real-time access to any node in the chip, with an easy-to-use GUI
interface. Designers verify chip functionality faster, without the added
overhead of testhead or bed-of-nails tests and fixtures. For high-density
devices, particularly in leadless packages, ChipScope ILA delivers real-time,
Xilinx is pioneering the design tools necessary to efficiently complete
million-gate and larger designs. Click
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