Name & Setting

Allows you to select an assignment name and setting for the specified nodes and entities.

Name	Setting
CDS Clock Phase	Default\|Negative 180\|Negative 90\| Zero\|Positive 90\|Positive 180
CLKLOCKx1 Input Frequency	On\|Off
Clock Enable Routing	Peripheral\|Single-Pin
Current Strength	Default Strength\|Min Strength\|Max Strength\|Strength 2mA\|Strength 4mA\|Strength 8mA\|Strength 12mA\|Strength 16mA\|Strength 24mA
Decrease Input Delay to Input Register	On\|Off
Decrease Input Delay to Internal Cells	On\|Off\|Large\|Medium\|Small
Decrease Input Delay to Output Register	On\|Off
DQS Delay	*<time>*
DQS Frequency	*<frequency>*
DQS Input Reference Clock	*<string>*
DQS Phase Shift	Phase of 90 degrees\|Phase of 72 degrees
Fast Input Register	On\|Off
Fast Output Enable Register	On\|Off
Fast Output Register	On\|Off
FastRow^™ Interconnect	On\|Off
FastRow Interconnect Delay	*<time>*
Global Signal	On\|Off
Implement as Output of Logic Cell	On\|Off
Increase Clock Enable Delay	On\|Off\|Large\|Small
Increase Delay to Output Enable Pin	On\|Off
Increase Delay to Output Pin	On\|Off
Increase Input Clock Enable Delay	Small\|Large\|On\|Off
Increase Output Clock Enable Delay	Small\|Large\|On\|Off
Increase Output Enable Clock Enable Delay	Small\|Large\|On\|Off
Increase tzx Delay to Output Pin	On\|Off
Input Reference	As VREFA\|As VREFB\|Off
Insert Additional Logic Cell	On\|Off
Local Routing Source	On\|Off
Logic Cell Insertion	*<integer>*
Manual Logic Duplication	*<string>*
Output Enable Register Duplication	On\|Off
Output Enable Routing	Peripheral\|Single-Pin
PLL Compensation	On\|Off
Row-Global Signal	On\|Off
Stratix^™ GX Termination Value	Off\|OCT 100 Ohms\|\|OCT 120 Ohms\|\|OCT 150 Ohms
Termination	Off\|Series\|Parallel\|Differential
Virtual Pin	On\|Off
Virtual Pin Clock	*<clock name>*

See the Description field for a description of options for nodes only.

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