Megafunction

lpm_mux, mux & busmux (Multiplexers) Megafunction

Parameterized multiplexer megafunctions. Altera® recommends that you use the lpm_mux function to replace all other multiplexer functions.

Altera also recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

The mux and busmux megafunctions are derived from lpm_mux, and are intended to simplify the use of lpm_mux in Block Design Files (.bdf):

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION lpm_mux (data[LPM_SIZE-1..0][LPM_WIDTH-1..0], sel[LPM_WIDTHS-1..0], clock, clken, aclr)
   WITH (LPM_WIDTH, LPM_SIZE, LPM_WIDTHS, LPM_PIPELINE)
   RETURNS (result[LPM_WIDTH-1..0]);

 

VHDL Component Declaration:

 
COMPONENT lpm_mux
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_SIZE: POSITIVE;
      LPM_WIDTHS: POSITIVE;
      LPM_PIPELINE: INTEGER:= 0;
      LPM_TYPE: STRING := "LPM_MUX";
      LPM_HINT: STRING := "UNUSED");
   PORT (data: IN STD_LOGIC_2D(LPM_SIZE-1 DOWNTO 0, LPM_WIDTH-1 DOWNTO 0);
      aclr, clock: IN STD_LOGIC := '0';
      clken: IN_STD_LOGIC := '1';
      sel: IN STD_LOGIC_VECTOR(LPM_WIDTHS-1 DOWNTO 0);
      result: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

COMPONENT busmux
   GENERIC (WIDTH: POSITIVE);
   PORT (dataa, datab: IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
      sel: IN STD_LOGIC;
      result: OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0));
END COMPONENT;

COMPONENT mux
   GENERIC (WIDTH: POSITIVE;
      WIDTHS: POSITIVE);
   PORT (data: IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
      sel: IN STD_LOGIC_VECTOR(WIDTHS-1 DOWNTO 0);
      result: OUT STD_LOGIC);
END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY lpm;
USE lpm.lpm_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
data[][] Yes Data input. Input port, consisting of LPM_SIZE buses, each LPM_WIDTH wide. Two-dimensional bus ports are not supported in Verilog HDL.
sel[] Yes Selects one of the input buses. Input port LPM_WIDTHS wide.
clock No Clock for pipelined usage. The clock port provides pipelined operation of the lpm_mux function. If an LPM_PIPELINE value other than 0 (default value) is specified, the clock port must be connected.
clken No Clock enable for pipelined usage. If omitted, the default is 1.
aclr No Asynchronous clear for pipelined usage. The pipeline initializes to an undefined (X) logic level. The aclr port can be used at any time to reset the pipeline to all 0's, asynchronously to the clock. However, the aclr port is used only if the LPM_PIPELINE parameter is specified (with a value other than 0) and the clock port is used.

OUTPUT PORTS

Port Name Required Description Comments
result[] Yes Selected input port. Output port LPM_WIDTH wide.

 

Parameter Descriptions:
Parameter Type Required Description
LPM_WIDTH Integer Yes Width of the data[][] and result[] ports.
LPM_SIZE Integer Yes Number of input buses to the multiplexer. LPM_SIZE <= 2 ^ LPM_WIDTHS.
LPM_WIDTHS Integer Yes Width of the sel[] input port.
LPM_PIPELINE Integer No Specifies the number of Clock cycles of latency associated with the result[] output. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. If omitted, the default is 0 (non-pipelined).
LPM_HINT String No Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). The default is "UNUSED".
LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files.

 

Truth Table/Functionality:

Each lpm_mux function defines LPM_WIDTH multiplexers. Each multiplexer has the following function:

Inputs Output
sel[LPM_WIDTHS-1..0] result[LPM_WIDTH-1]
0 data[0] [LPM_WIDTH-1..0]
1 data[1] [LPM_WIDTH-1..0]
2 data[2] [LPM_WIDTH-1..0]
... ...
LPM_SIZE-2 data[LPM_SIZE-2] [LPM_WIDTH-1..0]
LPM_SIZE-1 data[LPM_SIZE-1] [LPM_WIDTH-1..0]

This table assumes that LPM_SIZE is a power of two, although it is not required.

 

Resource Usage:

The following table summarizes the resource usage for an lpm_mux function used to implement a 16-to-1 multiplexer. Logic cell usage scales linearly in proportion to log(LPM_SIZE).

Design Goals Design Results
Device Family Optimization
APEX™ 20K Routability
  Speed
Width Logic Cells
16 13
16 10

Numbers of shared expanders used are shown in parentheses ( ).

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