You made pin assignments for a device. As a result, the output drivers between two GNDIO pins sink a total current exceeding 273mA. All output drivers between two GNDIO pins must sink a total current of 273mA or less. The current requirement for I/O standards with 3.3-V and 2.5-V V_CCIO levels are defined as follows:

For V_CCIO = 3.3V,

((<number of GTL+> × 36) + (<number of LVTTL> × I_LVTTL) + (<number of PCI> × 1.5) + (<number of LVCMOS> × I_LVCMOS) + (<number of SSTL-3 class I> × 8) + (<number of SSTL-3 class II> × 16) + (<number of LVDS> × 4.5) + (<number of AGP> × 1.5) + (<number of CTT> × 8)) mA <= 273mA

Where I_LVTTL (4 mA default value) and I_LVCMOS (0.1 mA default value) are the current sink on the LVTTL and LVCMOS pins, respectively.

For V_CCIO = 2.5V,

((<number of 2.5-V> × 2) + (<number of SSTL-2 class I> × 7.6) + (<number of SSTL-2 class II> × 15.2) mA <= 273mA

In practice, this rule applies only to SSTL-Class II, SSTL-3 Class II, GTL+, and LVCMOS and LVTTL I/O standard pins which can sink more than 14mA per output pin. For other standards, every pin can be used without violating this requirement.