Quartus

Fast or enhanced PLL clock output port <name> has illegal Global Signal logic option setting (<type>) -- must be set to Global Clock or Regional Clock

CAUSE: You assigned an illegal Global Signal logic option setting for the specified clock output port of a fast PLL or enhanced PLL. The PLL clock output port can only accept Global Clock or Regional Clock settings as Global Signal assignments.
ACTION: Delete or change the Global Signal logic option setting for the PLL clock output port.

See also:

Assigning Options for Individual Nodes Only
Changing Assignments
Deleting Assignments in the Assignment Organizer
Overview: Making Assignments

- PLDWorld -

 
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