CAUSE: | The Fitter cannot place the specified enhanced PLL because the PLL's input clocks and output clocks require more than the specified number of global clocks. This error may occur if you assign the Global Signal logic option to the output clock. |
ACTION: | Modify the design so that the specified PLL uses fewer global clocks, or delete the Global Signal logic option for the input and output clocks. |
- PLDWorld - |
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