Quartus

All destination nodes of output pin <name> of PLL <name> constrained to region <name>

CAUSE: The Fitter constrained all destination nodes of the specified PLL output pin to the specified region.
ACTION: No action is required. However, if you do not want the Fitter to constrain the nodes, assign the Global Signal logic option with the Global Clock setting to the specified output pin.

See also:

Overview: Making Assignments

- PLDWorld -

 
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