| CAUSE: | In the Test Bench file box in the Advanced Verilog HDL/VHDL Simulation Options dialog box, you did not specify a Verilog HDL test bench file name or a VHDL test bench file name. You cannot continue unless you specify a test bench file name, or select None or Command/macro mode. |
| ACTION: | Click OK to close the message dialog box, and then specify a legal test bench file name. |
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