| CAUSE: | In the Test Bench module name box in the Advanced Verilog HDL Simulation Options dialog box, you did not specify a test bench module name. You cannot continue unless you specify a test bench module name, or select None or Command/macro mode. |
| ACTION: | Click OK to close the message dialog box, and then specify a legal test bench module name. |
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |