| CAUSE: | In the current design, the Design Assistant found the specified number of input clock pins where each fans out to more than one gated clock (that is, an AND or OR gate that is synchronized with a register and used as a clock signal). However, an input clock pin should fan out to only one gated clock. The submessage(s) of this message list the pin(s) that the Design Assistant found. |
| ACTION: | Make sure each input clock pin fans out to only one gated clock. |
See also:
Analyzing Designs with the Design Assistant
Input Clock Pin Should Fan Out to Only One Gated Clock
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |